JPH0415627B2 - - Google Patents
Info
- Publication number
- JPH0415627B2 JPH0415627B2 JP57214254A JP21425482A JPH0415627B2 JP H0415627 B2 JPH0415627 B2 JP H0415627B2 JP 57214254 A JP57214254 A JP 57214254A JP 21425482 A JP21425482 A JP 21425482A JP H0415627 B2 JPH0415627 B2 JP H0415627B2
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- contact
- spacing
- resistance value
- sum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000008878 coupling Effects 0.000 claims description 6
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は集積回路装置で、とくに抵抗列を用い
て構成した電圧分圧回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and more particularly to a voltage divider circuit configured using a resistor string.
多数の基準抵抗を直列接続した抵抗列で比較用
基準電圧を作るＡ／ＤやＤ／Ａ変換器において、
半導体基板上の拡散領域又は半導体基板上に形成
した絶縁膜上に多結晶半導体領域を作り抵抗領域
を形成する。その抵抗領域上に一定間隔で金属配
線とコンタクトをとり、基準抵抗を直列接続した
抵抗分割形分圧回路を構成している。 In A/D and D/A converters that create a reference voltage for comparison using a resistor string consisting of a large number of reference resistors connected in series,
A polycrystalline semiconductor region is created on a diffusion region on a semiconductor substrate or an insulating film formed on a semiconductor substrate, and a resistance region is formed. Contact is made with metal wiring at regular intervals on the resistance region, and a resistance division type voltage dividing circuit is constructed in which a reference resistor is connected in series.
しかし、Ａ／Ｄ、Ｄ／Ａ変換器が高精度、高速
になるにつれて、基準抵抗を低抵抗にしなければ
ならず、コンタクト抵抗と基準抵抗の値が近づき
コンタクト抵抗の補正が必要となつてきた。 However, as A/D and D/A converters become more precise and faster, the reference resistance must be made lower in resistance, and the values of the contact resistance and the reference resistance become closer, making it necessary to correct the contact resistance. .
本発明の目的は、コンタクト抵抗を補正した抵
抗分割形分圧回路を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a resistor division type voltage divider circuit in which contact resistance is corrected.
本発明による抵抗列分圧回路は、拡散層または
多結晶半導体層で形成された抵抗領域を有し、第
１の電位が与えられた第１の配線が前記抵抗領域
の一端部分にある第１の結合部に接続され、第２
の電位が与えられた第２の配線が前記抵抗領域の
他端部分にある第２の結合部に接続され、前記第
１および第２の結合部の間にある複数の第３の結
合部から複数の第３の配線がそれぞれ導出されて
おり、さらに、前記第１および第２の結合部の面
積は共に前記の第３の結合部よりも大きくされ、
かつ前記第１の結合部とこれに隣接する第３の結
合部との第１の間隔および前記第２の結合部とこ
れに隣接する第３の結合部との第２の間隔は共に
前記第３の結合部同士の第３の間隔よりも小さく
なつていて、前記第１の結合部におけるコンタク
ト抵抗値と前記第１の間隔にもとづく抵抗値との
和、前記第２の結合部におけるコンタクト抵抗値
と前記第２の間隔にもとづく抵抗値との和、なら
びに前記第３の間隔にもとづく抵抗値は、互いに
実質的に等しくなつていることを特徴とする。 The resistor column voltage divider circuit according to the present invention has a resistor region formed of a diffusion layer or a polycrystalline semiconductor layer, and a first wiring to which a first potential is applied is located at one end of the resistor region. connected to the joint of the second
A second wiring to which a potential of A plurality of third wirings are each led out, and further, the areas of the first and second coupling portions are both larger than the third coupling portion,
and a first distance between the first joint portion and the third joint portion adjacent thereto and a second distance between the second joint portion and the third joint portion adjacent thereto are both equal to the first distance between the first joint portion and the third joint portion adjacent thereto. 3, the sum of the contact resistance value at the first joint part and the resistance value based on the first interval, and the contact resistance at the second joint part. The sum of the resistance value based on the second interval and the resistance value based on the third interval are characterized in that they are substantially equal to each other.
第１図に従来の集積回路に用いられている抵抗
分割形分圧回路を示す。 FIG. 1 shows a resistance division type voltage divider circuit used in a conventional integrated circuit.
第１図において、１は抵抗領域、２は金属配
線、３はコンタクトである。コンタクト間隔を一
定にとると、コンタクトａ−ｂ，ｂ−ｃ，ｃ−
ｄ，ｄ−ｅ間の抵抗は一定で基準抵抗値Ｒの抵抗
列が形成される。 In FIG. 1, 1 is a resistance region, 2 is a metal wiring, and 3 is a contact. If the contact spacing is constant, contacts a-b, b-c, c-
The resistance between d and d is constant, and a resistance string having a reference resistance value R is formed.
ここでコンタクトａ，ｂ，ｃ，ｄ，ｅのコンタ
クト抵抗をRCとするとこの抵抗列よりなる抵抗
分割分圧回路の等価回路は図２の様に記すことが
できる。 Here, if the contact resistances of contacts a, b, c, d, and e are R C , the equivalent circuit of the resistor division voltage divider circuit made up of this resistor array can be written as shown in FIG.
ここで端子V1を接地し、端子V5を基準電圧
VREFに接続すると、V1−V2間電圧は
｜V1−V2｜＝Ｒ＋RC／4R＋2RC・VREF ……(1)
となり、Ｒ≫RCの場合のみ各端子間電圧が均等
であるとみなす事ができる。しかし一例をあげる
と高速８ビツトＡ／Ｄ変換器では基準抵抗Ｒは約
40Ωであり、コンタクト抵抗RCは10Ω程度なの
で抵抗列の両端ではコンタクト抵抗の為に分圧回
路の出力電圧が内部端子のそれに較べて20％も違
つてしまう。又、同一スピードの10ビツトＡ／Ｄ
変換器を構成しようとする基準抵抗Ｒは約10Ω程
度となり50％もの誤差が生じ精度を保つ為には極
めてコンタクト抵抗の小さなコンタクト構造を用
いなければならず、複雑なプロセスが必要とな
る。 Here terminal V 1 is grounded and terminal V 5 is the reference voltage
When connected to V REF , the voltage between V 1 - V 2 becomes |V 1 - V 2 | = R + R C / 4R + 2R C・V REF ...(1), and the voltage between each terminal is equal only when R≫R C It can be considered that However, to give an example, in a high-speed 8-bit A/D converter, the reference resistance R is approximately
40Ω, and the contact resistance R C is about 10Ω, so the output voltage of the voltage divider circuit differs by 20% from that of the internal terminals due to the contact resistance at both ends of the resistor string. Also, 10-bit A/D at the same speed
The reference resistance R used to construct the converter is approximately 10Ω, resulting in an error of as much as 50%. In order to maintain accuracy, a contact structure with extremely low contact resistance must be used, and a complicated process is required.
第３図に本発明第１の実施例を、第４図に等価
回路を示す。 FIG. 3 shows a first embodiment of the present invention, and FIG. 4 shows an equivalent circuit.
抵抗領域の端部のコンタクトｆ，ｊを他のコン
タクトｇ，ｈ，ｉに較べて面積を４倍にすること
によつて、コンタクト抵抗を約1/4にし、かつ、
その端部のコンタクトとそれと隣接するコンタク
トすなわち、コンタクトｆ−ｇ、コンタクトｉ−
ｊの間隔l1を、他のコンタクトｇ−ｈ又はｈ−ｉ
間隔ｌに較べて、コンタクト抵抗に等しいだけ短
くしている。つまり端部のコンタクト抵抗RC1
と、その端部のコンタクトと、それと隣接するコ
ンタクトによつて作られる抵抗R1の和を、コン
タクトｆ−ｇ、ｉ−ｊで作られる抵抗と等しくし
ている。これによると(1)式は次の様になる。 By making the area of the contacts f, j at the end of the resistance region four times that of the other contacts g, h, i, the contact resistance is reduced to about 1/4, and
The contact at the end and the contacts adjacent thereto, i.e., contact f-g, contact i-
j distance l 1 from other contacts g-h or h-i
Compared to the spacing l, it is made shorter by an amount equal to the contact resistance. In other words, the contact resistance at the end R C1
The sum of the resistance R 1 created by the contact at the end and the contact adjacent thereto is equal to the resistance created by contacts fg and ij. According to this, equation (1) becomes as follows.
｜V2−V1｜＝R1＋RC1／２（Ｒ＋R1＋RC1）・VREF……
(2)
Ｒ＝R1＋RC1より
｜V2−V1｜＝１／４VREF ……(3)
となり誤差はなくなる。 ｜V 2 −V 1 ｜=R 1 +R C1 /2 (R + R 1 + R C1 )・V REF ......
(2) From R=R 1 +R C1 , |V 2 −V 1 |=1/4V REF ...(3) There is no error.
本発明は上記実施例に限らず、種々の形態をと
りうる。例えば、上記実施例では、抵抗領域の端
部のコンタクト数を１個で、面積を大きくしてい
るが、これに限らず第５図の様にある大きさの基
準コンタクトを複数個用い、その個数を、他のコ
ンタクトの個数より多くすれば実質的には、面積
として大きくなる。 The present invention is not limited to the above embodiments, and can take various forms. For example, in the above embodiment, the number of contacts at the end of the resistance region is one to increase the area, but this is not limited to this, and as shown in FIG. If the number of contacts is greater than the number of other contacts, the area will substantially increase.
第１図、第２図はそれぞれ従来例とその等価回
路図、第３図、第４図、第５図は本発明の実施例
を説明する図である。
１……抵抗領域、２……金属配線、３……コン
タクト部。
1 and 2 are diagrams of a conventional example and its equivalent circuit diagram, respectively, and FIGS. 3, 4, and 5 are diagrams for explaining an embodiment of the present invention. 1...Resistance region, 2...Metal wiring, 3...Contact portion.
Claims (1)
抗領域を有し、第１の電位が与えられた第１の配
線が前記抵抗領域の一端部分にある第１の結合部
に接続され、第２の電位が与えられた第２の配線
が前記抵抗領域の他端部分にある第２の結合部に
接続され、前記第１および第２の結合部の間にあ
る複数の第３の結合部から複数の第３の配線がそ
れぞれ導出されており、さらに、前記第１および
第２の結合部の面積は共に前記の第３の結合部よ
りも大きくされ、かつ前記第１の結合部とこれに
隣接する第３の結合部との第１の間隔および前記
第２の結合部とこれに隣接する第３の結合部との
第２の間隔は共に前記第３の結合部同士の第３の
間隔よりも小さくなつていて、前記第１の結合部
におけるコンタクト抵抗値と前記第１の間隔にも
とづく抵抗値との和、前記第２の結合部における
コンタクト抵抗値と前記第２の間隔にもとづく抵
抗値との和、ならびに前記第３の間隔にもとづく
抵抗値は、互いに実質的に等しくなつていること
を特徴とする抵抗列分圧回路。1 A first wiring having a resistance region formed of a diffusion layer or a polycrystalline semiconductor layer, to which a first potential is applied, is connected to a first coupling portion at one end of the resistance region, and a second A second wiring to which a potential of A plurality of third wirings are each led out, and furthermore, the areas of the first and second coupling portions are both larger than the third coupling portion, and the areas of the first and second coupling portions are The first spacing between the adjacent third bonding portion and the second spacing between the second bonding portion and the third bonding portion adjacent thereto are both equal to the third spacing between the third bonding portions. The sum of the contact resistance value at the first joint portion and the resistance value based on the first spacing, and the sum of the contact resistance value at the second joint portion and the resistance value based on the second spacing. A resistance string voltage divider circuit characterized in that the sum of the resistance values and the resistance values based on the third interval are substantially equal to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21425482A JPS59104159A (en) | 1982-12-07 | 1982-12-07 | Resistance row voltage dividing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21425482A JPS59104159A (en) | 1982-12-07 | 1982-12-07 | Resistance row voltage dividing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59104159A JPS59104159A (en) | 1984-06-15 |
| JPH0415627B2 true JPH0415627B2 (en) | 1992-03-18 |
Family
ID=16652707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21425482A Granted JPS59104159A (en) | 1982-12-07 | 1982-12-07 | Resistance row voltage dividing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59104159A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02161763A (en) * | 1988-12-14 | 1990-06-21 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JP5117817B2 (en) * | 2006-11-02 | 2013-01-16 | ルネサスエレクトロニクス株式会社 | Multi-level voltage generator, data driver, and liquid crystal display device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55148453A (en) * | 1979-05-08 | 1980-11-19 | Nec Corp | Semiconductor device |
-
1982
- 1982-12-07 JP JP21425482A patent/JPS59104159A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55148453A (en) * | 1979-05-08 | 1980-11-19 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59104159A (en) | 1984-06-15 |
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