JP3031582B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP3031582B2 JP3031582B2 JP4011838A JP1183892A JP3031582B2 JP 3031582 B2 JP3031582 B2 JP 3031582B2 JP 4011838 A JP4011838 A JP 4011838A JP 1183892 A JP1183892 A JP 1183892A JP 3031582 B2 JP3031582 B2 JP 3031582B2
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- semiconductor integrated
- integrated circuit
- circuit
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はＲ−２Ｒ方式のラダー回
路によるＤ／Ａコンバータ（Digital/AnalogConverto
r）を備える半導体集積回路に係り、特に高い変換精度
で高い歩留りのＤ／Ａコンバータを備える半導体集積回
路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter (Digital / Analog Converter) using an R-2R ladder circuit.
More particularly, the present invention relates to a semiconductor integrated circuit including a D / A converter with high conversion accuracy and high yield.
【０００２】近年のＤ／Ａコンバータには、高精度のも
のが要求されている。その為、製造上のバラツキに対し
ても、安定して高精度のものを製造する必要がある。In recent years, D / A converters have been required to have high accuracy. Therefore, it is necessary to stably manufacture high-precision products even with respect to manufacturing variations.
【０００３】[0003]
【従来の技術】Ｒ−２Ｒ方式のラダー回路を有して構成
され、１６ビットのディジタルデータをアナログデータ
に変換するＤ／Ａコンバータの等価回路を図３に示す。
また、従来のＤ／ＡコンバータのＲ−２Ｒ方式のラダー
回路の半導体集積回路上のレイアウトパターン図を図４
に示す。同図に示すように、従来では、抵抗を１０１及
び１０２（抵抗値２Ｒ）、１０３（抵抗値Ｒ）、１０４
及び１０５（抵抗値２Ｒ）、１０６（抵抗値Ｒ）、…と
配置して構成していた。すなわち、図５に示すように、
従来ではそれぞれ同一の抵抗体Ｒを所定ピッチで平行に
配列し、各抵抗Ｒを接続配線Ｍ０〜Ｍ７およびアルミ配
線Ｌ０〜Ｌ３、ＬＧ、ＬOUT を用いてラダー回路を構成
していた。2. Description of the Related Art FIG. 3 shows an equivalent circuit of a D / A converter configured to include an R-2R ladder circuit and converting 16-bit digital data into analog data.
FIG. 4 is a layout pattern diagram on a semiconductor integrated circuit of an R-2R ladder circuit of a conventional D / A converter.
Shown in As shown in the figure, conventionally, the resistors 101 and 102 (resistance 2R), 103 (resistance R), 104
And 105 (resistance 2R), 106 (resistance R),... That is, as shown in FIG.
Arranged in parallel to the same resistor R, respectively at a predetermined pitch in the conventional connection wires each resistor R M0 to M7 and aluminum wiring L0 to L3, LG, constituted the ladder circuit using L OUT.
【０００４】ところが、例えばエッチング工程における
寸法誤差等の製造プロセスのバラツキにより、全ての抵
抗を均一に製造することができない。或いは、半導体集
積回路の動作状態において、抵抗の近隣に熱源となる回
路が配置されていた場合には、抵抗が温度依存性を持つ
ために、抵抗値に誤差が生じるといった問題が生じる。
この場合、例えば、抵抗１０１の抵抗値がＲ−αに、抵
抗１０３の抵抗値がＲ＋αになったとすると、２Ｒ−
α：Ｒ＋αとなり、抵抗１０１及び１０２による２Ｒと
抵抗１０３によるＲの抵抗値の比を、正確に２：１にす
ることができず、Ｄ／ＡコンバータのＤ／Ａ変換精度を
悪化させる原因となっていた。However, all resistors cannot be manufactured uniformly due to manufacturing process variations such as dimensional errors in the etching process. Alternatively, in a case where a circuit serving as a heat source is arranged near the resistor in the operation state of the semiconductor integrated circuit, a problem occurs that an error occurs in the resistance value because the resistor has temperature dependency.
In this case, for example, if the resistance value of the resistor 101 becomes R-α and the resistance value of the resistor 103 becomes R + α, 2R−
α: R + α, and the ratio of the resistance value of 2R by the resistors 101 and 102 to the resistance value of R by the resistor 103 cannot be made exactly 2: 1, which causes the D / A conversion accuracy of the D / A converter to deteriorate. Had become.
【０００５】[0005]
【発明が解決しようとする課題】従って、高精度なＤ／
Ａ変換ができず、良品となる製造歩留りが低くなるとい
う問題があった。Therefore, a highly accurate D /
There is a problem that the A conversion cannot be performed and the production yield of a non-defective product decreases.
【０００６】本発明は、上記問題点を解決するもので、
製造バラツキが起きても、高い変換精度で高い歩留りで
製造可能なＤ／Ａコンバータを備える半導体集積回路を
提供することを目的とする。The present invention solves the above problems,
It is an object of the present invention to provide a semiconductor integrated circuit including a D / A converter that can be manufactured with high conversion accuracy and high yield even when manufacturing variations occur.
【０００７】[0007]
【課題を解決するための手段】上記課題を解決するため
に、本発明は、図１に示す如く、（Ｎは自然数）ビット
分のＲ−２Ｒ方式のラダー回路によるＮビットのＤ／Ａ
コンバータを備える半導体集積回路であって、同一の抵
抗値Ｒを有し、相互に平行に配置される複数の抵抗領域
１１〜１６を備えると共に、ｉ（ｉは２以上二つおきの
自然数）番目の抵抗領域１５を前記Ｒとし、ｉ−１番目
の抵抗領域１４とｉ＋１番目の抵抗領域１６を直列接続
して前記２Ｒとして構成した１ビット分のラダー回路を
Ｎビット分備える。In order to solve the above problems SUMMARY OF THE INVENTION The present invention, as shown in FIG. 1, (N is a natural number) bits
Of N bits by ladder circuit min R-2R type D / A
A semiconductor integrated circuit comprising a converter, having the same resistance value R, provided with a plurality of resistive regions 11 to 16 each other are arranged parallel to, i (i is 2 or more every three
The natural number) th resistance region 15 and the R, the i-1 th resistance region 14 and the (i + 1) th resistance region 16 connected in series to the ladder circuit for one bit configured as the 2R
N bits are provided .
【０００８】[0008]
【作用】本発明の半導体集積回路では、図１に示す如
く、同一の抵抗値Ｒを有する抵抗領域１１〜１６を、相
互に平行に配置し、ｉ（ｉは２以上二つおきの自然数）
番目の抵抗領域１５をＲとし、ｉ−１番目の抵抗領域１
４とｉ＋１番目の抵抗領域１６を直列接続して２Ｒとし
て構成した１ビット分のラダー回路をＮビット分備える
ようにしている。In the semiconductor integrated circuit according to the present invention, as shown in FIG. 1, resistance regions 11 to 16 having the same resistance value R are arranged in parallel with each other, and i (i is a natural number of every two or more).
The R-th resistance region 15 is defined as R, and the (i−1) -th resistance region 1
A 1-bit ladder circuit configured as 2R by connecting the 4th and (i + 1) th resistance regions 16 in series is provided for N bits .
【０００９】従って、エッチング工程における寸法誤差
等の製造プロセスのバラツキがある場合、或いは、抵抗
の近隣に熱源となる回路が配置されていた場合にも、各
ビットに対応するラダー回路を構成する抵抗２Ｒと抵抗
Ｒの抵抗値の比を、正確に２：１とすることができ、Ｄ
／Ａコンバータの各ビットにおけるＤ／Ａ変換精度を悪
化させることなく、全ビットに渡って高精度なＤ／Ａ変
換精度を有するＤ／Ａコンバータを高歩留りで製造する
ことができる。Accordingly, if there are variations in manufacturing processes, such as dimensional error in the etching process, or, even when close to the heat source circuit of the resistor has been arranged, each
The ratio of the resistance values of the resistors 2R and R constituting the ladder circuit corresponding to the bit can be made exactly 2: 1.
/ A converter without deteriorating the D / A conversion accuracy of each bit of a high-precision D / A variable over all bits
D / A converters having high conversion accuracy can be manufactured with high yield.
【００１０】[0010]
【実施例】次に、本発明に係る実施例を図面に基づいて
説明する。図１に本発明の一実施例に係る半導体集積回
路のパターン図を示す。Next, an embodiment according to the present invention will be described with reference to the drawings. FIG. 1 shows a pattern diagram of a semiconductor integrated circuit according to one embodiment of the present invention.
【００１１】同図に示すように、本実施例の半導体集積
回路は、同一の抵抗値Ｒを有する抵抗領域１１〜１６
を、相互に平行して配置して構成し、ｉ番目の抵抗領域
１５をＲとし、ｉ−１番目の抵抗領域１４（抵抗値２Ｒ
／２）とｉ＋１番目の抵抗領域１６（抵抗値２Ｒ／２）
を直列接続して２Ｒとして１ビット分のラダー回路を構
成するようにしている。As shown in FIG. 1, the semiconductor integrated circuit of this embodiment has resistance regions 11 to 16 having the same resistance value R.
Are arranged in parallel with each other, the i-th resistance region 15 is defined as R, and the (i−1) -th resistance region 14 (resistance value 2R
/ 2) and the (i + 1) th resistance region 16 (resistance value 2R / 2)
Are connected in series to form a 1-bit ladder circuit as 2R.
【００１２】すなわち、詳しては図２に示すように、平
行に配された複数の抵抗領域（ポリシリコン等）Ｒの各
端部をコンタクトホールＣＨを介して接続配線領域（ア
ルミニウム等）により図１の回路になるよう接続したも
のである。図中、ＬＧは接地ＧＮＤへの配線（アルミニ
ウム等）、Ｌ０〜Ｌ３は各ビットドライバへの配線（ア
ルミニウム等）、ＬOUT はＤ／Ａ出力端子配線（アルミ
ニウム等）を示している。More specifically, as shown in FIG. 2, each end of a plurality of resistance regions (polysilicon or the like) R arranged in parallel is connected by a connection wiring region (aluminum or the like) through a contact hole CH. One circuit is connected. In the figure, LG shows the wiring to the ground GND (aluminum, etc.), L0 to L3 wiring to each bit driver (such as aluminum), L OUT is D / A output terminal wiring (aluminum).
【００１３】このような構成とすることにより、エッチ
ング工程における寸法誤差等の製造プロセスのバラツキ
がある場合、或いは、抵抗の近隣に熱源となる回路が配
置されていた場合に、例えば、抵抗１４の抵抗値が２Ｒ
／２−αに、抵抗１６の抵抗値が２Ｒ／２＋αになった
とすると、誤差は相殺されて２Ｒ：Ｒとなり、抵抗１４
及び１６による２Ｒと抵抗１５によるＲの抵抗値の比
を、正確に２：１にすることができ、Ｄ／Ａコンバータ
のＤ／Ａ変換精度を悪化させることなく、高精度なＤ／
Ａコンバータを高歩留りで製造することができる。With such a configuration, when there is a variation in the manufacturing process such as a dimensional error in an etching process, or when a circuit serving as a heat source is arranged near the resistor, for example, Resistance value is 2R
Assuming that the resistance value of the resistor 16 becomes 2R / 2 + α, the error is canceled out to be 2R: R, and the resistance 14
The ratio of the resistance value of 2R by R and 16 to the resistance value of R by the resistor 15 can be made exactly 2: 1 and the D / A conversion accuracy of the D / A converter is not deteriorated, and the D / A conversion accuracy is high.
The A converter can be manufactured with a high yield.
【００１４】[0014]
【発明の効果】以上説明したように、本発明によれば、
同一の抵抗値Ｒを有する抵抗領域を、相互に平行に配置
して構成し、ｉ番目の抵抗領域をＲとし、ｉ−１番目の
抵抗領域とｉ＋１番目の抵抗領域を直列接続して２Ｒと
して構成した１ビット分のラダー回路をＮビット分備え
るようにしたので、エッチング工程における寸法誤差等
の製造プロセスのバラツキがある場合、或いは、抵抗の
近隣に熱源となる回路が配置されていた場合にも、各ビ
ットに対応するラダー回路を構成する抵抗２Ｒと抵抗Ｒ
の抵抗値の比を、正確に２：１とすることができ、Ｄ／
Ａコンバータの各ビットにおけるＤ／Ａ変換精度を悪化
させることなく、全ビットに渡って高い変換精度を有
し、且つ高歩留りで製造可能なＤ／Ａコンバータを備え
る半導体集積回路を提供することができる。As described above, according to the present invention,
The resistance regions having the same resistance value R are arranged in parallel with each other, the i-th resistance region is defined as R, and the (i-1) -th resistance region and the (i + 1) -th resistance region are connected in series as 2R. Equipped with N bits of configured 1-bit ladder circuits
Since so that, if there are variations in manufacturing processes, such as dimensional error in the etching process, or, even when close to the heat source circuit of the resistor has been arranged, the bi
2R and R that constitute a ladder circuit corresponding to
Can be made exactly 2: 1, and D /
Without deteriorating the D / A conversion accuracy of each bit of the A converters, have a high conversion accuracy over the entire bit
In addition, it is possible to provide a semiconductor integrated circuit including a D / A converter that can be manufactured with a high yield.
【図１】本発明の一実施例に係る半導体集積回路のラダ
ー回路部分のレイアウトパターン図である。FIG. 1 is a layout pattern diagram of a ladder circuit portion of a semiconductor integrated circuit according to one embodiment of the present invention.
【図２】本発明のラダー回路部分のレイアウトパターン
の詳細例を示す図である。FIG. 2 is a diagram showing a detailed example of a layout pattern of a ladder circuit portion of the present invention.
【図３】Ｒ−２Ｒ方式のラダー回路によるＤ／Ａコンバ
ータの等価回路図である。FIG. 3 is an equivalent circuit diagram of a D / A converter using an R-2R ladder circuit.
【図４】従来の半導体集積回路のラダー回路部分のパタ
ーン図である。FIG. 4 is a pattern diagram of a ladder circuit portion of a conventional semiconductor integrated circuit.
【図５】従来のラダー回路部分のレイアウトパターンの
詳細例を示す図である。FIG. 5 is a diagram showing a detailed example of a layout pattern of a conventional ladder circuit portion.
１１〜１６、１０１〜１０６…抵抗領域 Ｒ、２Ｒ、Ｒｆ…抵抗 ＡＭＰ…オペアンプ 11 to 16, 101 to 106: resistance region R, 2R, Rf: resistance AMP: operational amplifier
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H03M 1/00 - 1/88 H01L 27/04 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H03M 1/00-1/88 H01L 27/04
Claims (1)
式のラダー回路によるＮビットのＤ／Ａコンバータを備
える半導体集積回路であって、 同一の抵抗値Ｒを有し、相互に平行に配置される複数の
抵抗領域（１１〜１６）を備えると共に、 ｉ（ｉは２以上二つおきの自然数）番目の抵抗領域（１
５）を前記Ｒとし、ｉ−１番目の抵抗領域（１４）とｉ
＋１番目の抵抗領域（１６）を直列接続して前記２Ｒと
して構成した１ビット分のラダー回路をＮビット分備え
ることを特徴とする半導体集積回路。1. A semiconductor integrated circuit comprising an N-bit D / A converter using an R-2R ladder circuit for N (N is a natural number) bits , having the same resistance value R and being parallel to each other. And a plurality of resistance regions (11 to 16) arranged in the i-th (i is a natural number of 2 or more every 2) th resistance region (1
5) and the R, i-1-th resistor region (14) and i
+1 th ladder circuit for one bit which constitutes the resistive region (16) as the 2R connected in series N bits comprises
The semiconductor integrated circuit, characterized in that that.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4011838A JP3031582B2 (en) | 1992-01-27 | 1992-01-27 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4011838A JP3031582B2 (en) | 1992-01-27 | 1992-01-27 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05206863A JPH05206863A (en) | 1993-08-13 |
| JP3031582B2 true JP3031582B2 (en) | 2000-04-10 |
Family
ID=11788877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4011838A Expired - Fee Related JP3031582B2 (en) | 1992-01-27 | 1992-01-27 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3031582B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69828374T2 (en) | 1997-07-03 | 2005-12-08 | Seiko Epson Corp. | LADDER RESISTANCE CIRCUIT AND DIGITAL / ANALOG CONVERTER AND THUS EQUIPPED SEMICONDUCTOR DEVICE |
| JP3281621B2 (en) * | 1999-12-21 | 2002-05-13 | 松下電器産業株式会社 | High precision DA conversion circuit |
-
1992
- 1992-01-27 JP JP4011838A patent/JP3031582B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05206863A (en) | 1993-08-13 |
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