JP2604374B2 - Analog-to-digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a parallel type analog / digital (hereinafter, referred to as A / D) converter.

[Conventional technology]

As is well known, the all-parallel A / D converter has a configuration as shown in FIG. 5, in which a reference voltage V _{REF is connected} to 2 ⁿ reference resistors R ₁ and R ₁ .
_A reference resistance ladder circuit composed of ₂ , R ₃ ... R ₂ ⁿ divides the voltage into 2 ⁿ equal parts, and divides each voltage into (2 ⁿ −1) parallel-connected comparators C ₁ , C ₂ , C ₃ ... A reference voltage input of C ₂ ⁿ _-1 is compared with an analog input signal. The output of the comparator is output as a digital signal D ₁ -Dn of n bits are encoded by the encoder circuit.

For example, if the resolution is 8 bits, 256 reference resistors and 2
55 comparators are required. The value of the reference resistor needs to be reduced in proportion to the resolution in order to avoid the influence of the input current of the comparator. In the case of 8-bit resolution, the value is about 0.2Ω. Therefore, aluminum wiring resistance is usually used.

FIG. 4 is a main block layout diagram of this type of conventional A / D converter, and shows a plan view of an 8-bit A / D converter. In the figure, 256 comparator blocks C _{1 to} C ₂₅₆ (not shown) including overflow are arranged in a matrix of 32 rows × 8 columns, and are divided into 4 blocks of 2 columns each. , the output of each of the comparators C ₁ -C ₂₅₆ is encoded into 8 bits by an encoder block EC5 after being coded respectively by the encoder block EC1~4 6-bit binary code is output to the outside by the output buffer OB You.

A reference resistance ladder composed of ₂₅₆ reference resistances R _{1 to} R ₂₅₆ (partly not shown) is arranged seven times between comparators divided into four corresponding to the above four blocks, and is wired. W ₁ 〜
And it is connected to the comparator by W _256. Reference resistance R _{1 to} R
₂₅₆ and the wirings W _{1 to} W ₂₅₆ are formed of the same aluminum, and usually,
The first layer is made of aluminum.

Wirings for power supply, ground, clock, analog input, etc. are usually formed of second-layer aluminum and arranged on the comparator block as common wiring of the comparator block (not shown).

[Problems to be solved by the invention]

In the above-described conventional A / D converter, since the reference resistor is arranged over the entire chip, it is difficult to increase the relative accuracy. On the other hand, there is a close relationship between the relative accuracy of the reference resistor and the linearity error of the A / D converter. However, there are problems such as a decrease in yield and an increase in cost. In particular, as can be seen from FIG. 4, the positions of the reference resistors are separated by about 1 mm before and after the first, third, fifth, and seventh folded portions of the reference resistor ladder, so that the relative accuracy in the X direction in the figure is poor. There is a problem that the linearity error is largely shifted by 1 LSB or 1 LSB.

Further, since the shape of the folded portion is very large, there is a problem that the chip area is significantly increased. This is because one reference resistor is formed including the folded portion, so that the resistance occupied by the folded portion must be as small as possible in order to ensure relative accuracy with other reference resistors. . For example, in the case of 8-bit resolution, the unit reference resistance is about 0.2 ohm. To make the value R at the folded portion 40 mΩ, which is 1/5 of this value, the aluminum layer resistance ρ _S = 20 mohm and the length L of the folded portion Is 90 micrometers, W = (L /
R) [rho folded portion Aluminum width W by the expression of _S is also 450 micrometers.

Compared to the conventional A / D converter described above, the A / D converter of the present invention can improve the linearity error even if the thickness of the aluminum film or the width of the reference resistance occurs in the processing step. ,
It has an original content that the chip area can be made smaller than before.

[Means for solving the problem]

An A / D converter according to the present invention includes a semiconductor substrate on which a plurality of comparator blocks, a reference resistance ladder in which substantially the same number of reference voltage generating resistors as the comparator blocks are connected in series, and an encoder block are arranged. In the formed parallel type analog-digital converter, the comparator blocks are arranged at least two in the vertical direction and a large number in the horizontal direction with respect to the reference resistance ladder on both sides of the reference resistance ladder arranged one turn substantially in the center, The connection between the reference voltage input of the comparator block and the reference voltage generating resistor is sequentially performed from the comparator block arranged in the vertical direction, and this is repeated in the horizontal direction.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of an A / D converter showing a first embodiment of the present invention.

The 256 reference resistances R _{1 to} R ₂₅₆ (partly not shown) are arranged by being folded only once at the center of the chip, and 256 comparator blocks C _{1 to} C ₂₅₆ (partly not shown) Are arranged on both sides of the reference resistance ladder by 64 rows × 2 columns.

The comparator block is divided into four blocks in an upper half and a lower half, and each output is made up of 6 bits of 2 bits by encoder blocks EC1 to EC4 arranged on the output side of the comparator block.
After being encoded into a hexadecimal code, it is encoded into 8 bits by the encoder block EC5 and output to the outside by the output buffer OB.

Each of the comparator blocks C _{1 to} C ₂₅₆ has at least one wiring passage area in the horizontal direction and the vertical direction, and the horizontal wiring passage area of the comparator block C ₂ has the reference voltage input terminal of the comparator block C ₁ and the reference. resistance wiring W ₁ for connecting the one end of the R ₂ is disposed in the horizontal direction line passing region of the comparator block C ₁ connects the input terminal of the output terminal of the comparator block C ₂ and the encoder block EC1 wiring L ₂ are located. Further reference voltage input terminal of the comparator block C ₂ is connected to the other end of the reference resistor R ₂ by a wire W _2, the output terminal of the comparator block C ₁ is connected to the other input terminal of the encoder block by wiring L ₁ Have been. Hereinafter, it has been implemented similar connected comparator block C ₃ -C _256.

Also, as in the conventional, the vertical direction line passing region of the comparator block C ₁ -C ₂₅₆ (not shown) power, ground, clock, common wirings such as the analog input is arranged for each column. The wiring passage area of the comparator block can be easily realized by selectively using the first layer aluminum in the horizontal direction, the second layer aluminum in the vertical direction, and the first layer aluminum in the block.

According to the figure, it is necessary to arrange two reference resistors R _{1 to} R ₂₅₆ within the vertical dimension of the comparator block, but if the resistance length is insufficient, bend and arrange as shown in FIG. Good.
Although the whole comparator is divided into four blocks, it may be divided into two blocks on the basis of the reference resistance ladder. In this case, the encoder blocks EC1 and EC2 and the encoder blocks EC3 and EC4 are collectively converted into a 7-bit code. Should be changed to Further comparators C ₁ and C _2, C ₃ and C _4, ... may be reversed each a relationship C ₂₅₅ and C _256, this case may be changed also hardwired.

In the above-described A / D converter of the present invention, since the reference resistance ladder can be disposed only at the center of the chip by one turn, the reference resistance is not disposed on the entire chip as in the conventional example. Therefore, even if a change in the aluminum film thickness or a change in the resistance width occurs in the chip, a decrease in the accuracy of the resistance attachment is small and the linearity error is improved. In particular, the improvement in the change in the horizontal direction (X direction) is remarkable, and the linearity error is 5 bits to 6 bits as in the conventional case.
There is no significant change in bit units.

In addition, since the reference resistor ladder can be placed in the center of the chip, it is more advantageous than conventional products in reducing resistance accuracy due to distortion during resin sealing, reliability characteristics such as aluminum corrosion, and resistance value deviation due to temperature difference on the chip. It is.

Further, since there is no portion which takes a very large area for connection unlike the first, third, fifth and seventh folded portions of the conventional reference resistance ladder, the chip area is reduced by reducing the area of this portion. In addition, there is essentially no linearity error caused by the fact that the aluminum width of the folded portion is significantly different from the widths of the other reference resistors, which is very advantageous over the prior art.

Next, the present example is also effective in improving the linearity error, particularly the differential linearity error, as compared with the conventional example, even with respect to changes in the aluminum film thickness in the vertical direction (Y direction) in the chip. This is because while the conventional reference resistor is arranged at a ratio of one in the vertical dimension of the comparator block, in the present invention, it is arranged twice in the vertical direction. On the other hand, the deviation of the relative ratio of the adjacent reference resistance is reduced to half of the conventional value.

FIG. 3 shows an A / D converter according to a second embodiment of the present invention.

In the figure, 256 comparator blocks C _{1 to} C ₂₅₆ (partially not shown) are arranged on both sides of reference resistors R _{1 to} R ₂₅₆ (partially not shown) by 32 rows × 4 columns. , Comparator block C ₄
Wirings W ₁ , W ₂ , and W ₃ are arranged in the horizontal wiring passing area of, and the wirings W ₁ , W _2, and L ₄ are arranged in the horizontal wiring passing area of the comparator block C _3. , comparator laterally line passing area of the block C ₂ is arranged the wiring W _1, L ₄ and the wiring L _3, comparator said laterally line passing area of the block C ₁ lines L _4, L ₃ L ₂ are located.

Further, the comparator reference voltage input terminal of the block C ₄ is connected to the connection point of the reference low anti R ₅ and R ₄ by a wire W _4, the output terminal of the comparator block C ₁ encoder block by wiring L ₁ EC1
Is connected to the input terminal of Wiring W ₁ is a comparator block
A reference voltage input terminal of the C _1, connects the connection point of the reference resistor R ₁ and R _2, likewise the wiring W ₂ is the reference voltage input terminal of the comparator block C _2, the reference resistor R ₂ and R ₃ a connection point, the wiring W ₃ being connected to the reference voltage input terminal of the comparator block C _3, the reference resistor R ₃ and R ₄ the connection point.

The wiring L ₂ is comparator input of the output terminal of the block C ₂ and the encoder block EC1, wiring L ₃ is a comparator input of the output terminal and the encoder block EC1 block C _3, wire L ₄ represents a comparator block C ₄ The output terminal is connected to the input of the encoder block EC1.

The inputs of the encoder blocks are the same as the number of comparator blocks and are independent. Hereinafter, the comparator blocks C ₅ and C
_6, C _7, C ₈ and C ₉ -C ₂₅₆ same wiring is performed (not shown). Further, in the first embodiment in the vertical wires passing region of the comparator block C ₁ -C _256, the common wirings are arranged and wired in the same manner (not shown).

In the A / D converter of the second embodiment described above, four reference resistors are arranged in the vertical dimension of the comparator block.
The linearity error can be improved as compared with the first embodiment with respect to the change in the aluminum film thickness and the change in the resistance width in the vertical direction of the chip. Further, by increasing the number of comparator blocks in the vertical direction to 64 rows x 4 columns, the encoder block can be easily modified by modifying the encoder block.
This has the advantage that a bit A / D converter can be realized. Even in this case, the effect of improving the linearity error is the same as in the case of the 8-bit A / D converter.

〔The invention's effect〕

As described above, the present invention provides a comparator block of an all-parallel A / D converter by providing vertical and horizontal wiring passage areas to improve the arrangement and wiring of the comparator block and the reference resistance ladder. This has the effect of improving the relative ratio accuracy of the reference resistance ladder and realizing a high-precision A / D converter with a smaller chip area, and the effect of easily achieving high resolution.

[Brief description of the drawings]

1 is a first embodiment of the present invention, FIG. 2 is a plan view of a reference resistor in the present embodiment, FIG. 3 is a second embodiment of the present invention, FIG. 4 is a conventional example and FIG. Is a circuit block diagram of a general parallel A / D converter. C _{1 to} C ₂₅₆ …… Comparator block, R _{1 to} R ₂₅₆ …… Reference resistance,
W _{1 to} W ₂₅₆ , L _{1 to} L ₂₅₆ ... wiring, EC1 to EC5 ... encoder block, OB ... output buffer.

Claims (1)

(57) [Claims] A parallel analog circuit formed by arranging a plurality of comparator blocks, a reference resistor ladder having substantially the same number of reference voltage generating resistors connected in series with the comparator blocks, and an encoder block on a semiconductor substrate. In the digital converter, at least two comparator blocks are arranged on both sides of the reference resistor ladder, which is arranged at one turn substantially in the center, at least two in the vertical direction, and a plurality of comparator blocks are arranged in the horizontal direction. An analog-to-digital converter wherein connection between a reference voltage input of a block and the reference voltage generating resistor is sequentially performed from a comparator block arranged in a vertical direction, and this is repeated in a horizontal direction.