JPH057160A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To improve the yield by reducing the dispersion in the accuracy between D/A converters when plural D/A converters are formed in one-chip. CONSTITUTION:Plural D/A converters 1-3 are formed in a chip 6 and high-order bit constant current sources 1A,3A of the D/A converters 1,3 are arranged close to the middle of the chip. The distance of the D/A converters 1,3 from the chip end 4 is made almost identical to each other by increasing the size of the chip end 4 of the D/A converter 1, interposing a common circuit block 5 or replacing the high-order bit constant current source with the low-order bit constant current source 1B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog converter, and more particularly to a digital / analog converter (hereinafter referred to as DA converter) in which a plurality of digital / analog converters (hereinafter referred to as DA converters) are integrated on the same semiconductor substrate. (Referred to as a DA converter).

[0002]

2. Description of the Related Art Conventionally, this type of DA converter has been constructed using a constant current source and a current switch.

FIG. 4 is a block diagram of such a conventional DA converter. As shown in FIG. 4, the conventional DA converter includes an input buffer 7, a decoder 8 and a clock synchronization circuit 9, a constant current source 10, a current switch 11 and a ladder resistor 12,
It has a clock buffer 13 for inputting a clock. In this example, the upper 3 bits (D1 to D3) are decoder 8
The current addition type that sequentially connects the seven constant current sources and the current switch to the analog output is adopted, and the lower 5 bits (D4
D8) adopts an R-2R ladder resistance type to form an 8-bit DA converter. The input buffer 7 is a circuit for converting a digital input signal level into an internal logic level, and the upper 3 bits are the decoder circuit 8 described above.
Is input to the clock synchronization circuit 9 via
The bits are directly input from the input buffer 7 to the clock synchronization circuit 9. The clock synchronizing circuit 9 settles digital data in synchronization with a clock signal applied from the outside,
The current switch 11 is switched according to the input level to obtain a predetermined analog output.

In recent years, with the digitization of image equipment, it has become necessary to integrate a plurality of such DA converters into one chip. For example, R / G / B for driving CRT of TV receiver
Digitizing a signal requires three DA converters.

FIG. 5 is a block layout diagram of a DA conversion device showing a conventional example using the DA converter shown in FIG.
As shown in FIG. 5, the DA converter (for Rch) 1 is a block 1A consisting of a high-order bit constant current source and a current switch, a block 1B consisting of a low-order bit constant current source and a current switch, an input buffer 7, and a degoder of FIG. 8, block 1 including clock synchronization circuit 9 and clock buffer 13
It is composed of C and. Further, a DA converter 2 (for Gch) and a DA converter (Bch) having the same configuration as this DA converter 1
3) is arranged, and the common part of these DA converters 1 to 3,
For example, a common circuit block 5 in which a bias circuit of a constant current source circuit, an analog output voltage adjusting amplifier, a clock buffer, and the like are arranged, and a bonding pad for connecting to an external terminal of an outer peripheral portion 4 of a chip 6 is provided. And the common power supply wiring is arranged. Although the DA converters 1 to 3 are R, G, and B channels, they are not limited to this arrangement.

FIG. 6 is a circuit diagram of the constant current source shown in FIGS. 4 and 5. As shown in FIG. 6, the constant current source circuit 15 of the conventional DA converter has a transistor Q3 and a resistor R, and is connected to a current switch circuit 14 including transistors Q1 and Q2. Regarding the circuit operation,
Since it is well known, its explanation is omitted.

[0007]

The conventional DA converter described above has a drawback that a differential linearity error becomes large in a digital code for switching the constant current source of the upper bit and the constant current source of the lower bit after resin sealing. is there. In particular, D
It has been found that the differential linearity error of the A converter 1 is larger than that of the other DA converters 2 and 3.

The reason why the differential linearity error becomes large at the time of switching between the high-order and low-order bit constant current sources is as follows.

For example, when the code 00011111 is changed to the code 00100000, the former is a constant current source for lower 5 bits connected to an analog output to generate a predetermined analog output voltage, and the latter is one constant current source for upper bits. Only one of them is connected to the analog output to generate the analog output voltage of 1 LSB added, but the 12 constant current sources have slightly different positions on the chip, and thus the output currents are slightly different. Therefore, when the code is switched, the position of the constant current source connected to the analog output largely changes, and the error also increases. That is, this is because the output current of the constant current source circuit changes due to the deviation of the ratio of the emitter resistance R of the constant current source transistor Q3 given the common bias potential VB.

Similarly, the code (00111111 → 0100) before and after the second constant current source of the upper bit is connected.
0000) and the code before and after the third constant current source of the upper bit is connected (01011111 → 011000
00) causes an error, and also occurs every 32 codes.

Next, the reason why the differential linearity error of the DA converter 1 becomes larger than that of the other DA converters 2 and 3 is that the constant current source 1A of the upper bit of the DA converter 1 shown in FIG. It is arranged on the chip outer peripheral portion 4 side, and the distance y1 from the chip end portion is the distance y between the DA converters 2 and 3 of other channels.
This is because it is smaller than 2 etc., and therefore the change in the emitter resistance of the constant current source circuit due to the stress on the chip that occurs during resin sealing is larger than in other channels. Therefore, the difference between the output currents of the high-order bit constant current source and the low-order bit constant current source becomes larger than that of the other channels, and the error at the time of code change described above becomes larger than that of the other channels. As described above, when a plurality of DA converters are integrated into a single chip, if any one of the DA converters does not satisfy the characteristics, the chip must be regarded as a defective product. Will be lowered.

An object of the present invention is to provide a DA converter which eliminates the difference in various accuracies between the DA converters even when the plurality of DA converters are integrated into one chip and improves the manufacturing yield. To do.

[0013]

SUMMARY OF THE INVENTION A DA converter of the present invention comprises a DA converter on a semiconductor substrate, in which a plurality of constant current sources and switches are connected in parallel corresponding to the weight of bits, and the operation weights the current. A plurality of DA converters each having an upper bit and a lower bit constant current source and a circuit block and arranged in one direction on the semiconductor substrate.
The DA converters at both ends of the converter are arranged such that the upper bit constant current source and the end of the semiconductor substrate are substantially equal in distance.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block layout diagram of a DA converter according to a first embodiment of the present invention. As shown in FIG. 1, in this embodiment, three DA converters 1 to
3 shows a case where 3 is integrated into one chip, the DA converter 1 includes a high-order bit constant current source block 1A including a constant current source and a current switch, a low-order constant current source block 1B including a constant current source and a current switch, The circuit block 1C includes an input buffer, a decoder, a clock synchronization circuit, and a clock buffer. Also, the DA converters 2 and 3 have the same configuration as the DA converter 1, and
The point of being arranged in one direction of the chip and the point of forming the common common block 5 in one direction of the outer peripheral portion 4 of the chip 6 are the same as in the conventional example. The present embodiment is different from the above-mentioned conventional example in that the distance y1 from the upper bit constant current source 1A of the DA converter 1 to the chip end and the distance from the upper bit constant current source 3A of the DA converter 3 to the chip end. The three DA converters 1 to 3 are arranged so that the distance y2 is almost the same. With such an arrangement, the same amount of differential linearity error occurs when the upper and lower bits of the DA converter 1 and the DA converter 3 are switched, so that only the DA converter 1 as in the conventional example is generated. It is possible to prevent the error of from becoming large. That is, the stress generated when the chip 6 is sealed with resin is D
The same degree of change occurs in the direction of the A converter 3, and the output currents of both upper bit constant current sources 1A and 3A change in the same direction in the opposite direction. Therefore, only one DA converter has an error. Does not grow. Further, the lower bit constant current source 3B of the DA converter 3 is closer to the chip end as compared with the conventional example, but the output current of the lower bit constant current source is R-2R ladder resistance. 1
In 2 (see FIG. 4), the voltage is divided into ½ every 1 bit down, so the influence of the shift of the constant current source is reduced toward the lower bit, and the error is less likely to occur.

FIG. 2 is a block layout diagram of a DA converter according to the second embodiment of the present invention. As shown in FIG. 2, this embodiment shows a case where three DA converters are integrated into one chip as in the first embodiment, and the upper bit constant current source 2A of the DA converter 2 is arranged in the center of the chip. , DA converter 1
The point that the distances between the upper bit constant current sources 1A and 3A of the DA converter 3 and the chip end are the same as in the first embodiment described above. The present embodiment is different from the first embodiment in that the distance between the upper bit constant current source 1A of the DA converter 1 and the end of the chip and the upper bit constant current source 3A of the DA converter 3 and the chip are different. The common circuit block 5 is arranged in a region provided to make the distance between the end portions the same. With this arrangement, the internal area of the chip 6 can be used, and the same effect as the first embodiment can be obtained with the same chip size as the conventional example.
The common circuit block 5 may be provided with circuits other than the high-order bit constant current sources 1A to 3A constituting the DA converters 1 to 3.

In the above embodiment ,. Although the description has been made with the center of the upper bit constant current source of the DA converter as a reference, the same effect can be obtained even if the boundary or center of the upper bit is slightly shifted.

FIG. 3 is a block layout diagram of a DA converter according to the third embodiment of the present invention. As shown in FIG. 3, this embodiment also shows an example in which the three DA converters 1 to 3 are integrated into one chip as in the above-described first and second embodiments. The difference lies in the DA converter. 1 upper bit constant current source 1A
And the arrangement of the lower bit constant current source 1B is opposite to the arrangement of the upper bit constant current sources 2A and 3A and the lower bit constant current sources 2B and 3B of the DA converters 2 and 3, respectively. By arranging in this way, the high-order bit constant current sources 1A and 3A of the DA converter 1 and the DA converter 3 are equidistant from the chip end, which is the same as the first and second embodiments described above. The effect can be obtained. In addition, the present embodiment can make the chip size smaller than that of the first embodiment, and the common circuit block 5 and the DA converter 1 to DA converter 3 can have the same precision relationship.

[0019]

As described above, in the DA converter of the present invention, when a plurality of DA converters are integrated on a semiconductor substrate, the position of the upper bit constant current source circuit of the central DA converter is set on a chip. Differentiating a specific DA converter by arranging it in the center with respect to one direction and arranging the positions of the constant-current source circuits of the high-order bits of the DA converter at both ends in the same direction from both ends of the chip when viewed in the one direction. There is an effect that it is possible to prevent a decrease in linearity accuracy. This can improve the manufacturing yield.

Further, according to the present invention, since the deterioration of the differential linearity accuracy of the DA converter due to the resin stress can be made uniform, the characteristics among the DA converters can be easily made uniform, and further the internal circuit constituting the DA converter can be made. Since it is not necessary to provide the position of (3) in another DA converter, there is an effect that the differential linearity characteristic between the DA converter and the DA converter can be improved.

[Brief description of drawings]

FIG. 1 is a block layout diagram of a DA converter according to a first embodiment of the present invention.

FIG. 2 is a block layout diagram of a DA converter according to a second embodiment of the present invention.

FIG. 3 is a block layout diagram of a DA converter according to a third embodiment of the present invention.

FIG. 4 is a configuration diagram of a conventional DA converter.

5 is a block layout diagram of a DA conversion device showing a conventional example using the DA converter in FIG.

FIG. 6 is a circuit diagram of the constant current source in FIGS. 4 and 5.

[Explanation of symbols]

1,2,3 DA converter 1A, 2A, 3A Upper bit constant current source block 1B, 2B, 3B Lower bit constant current source block 1C, 2C, 3C circuit block 4 chip periphery 5 Common circuit block 6 chips

Claims (3)

[Claims] 1. A digital-analog converter in which a plurality of constant-current sources and switches are connected in parallel corresponding to bit weights and current-weighting is carried out by the operation thereof on a semiconductor substrate. The device includes a plurality of digital / analog converters each having a high-order and low-order bit constant current source and a circuit block and arranged in one direction on the semiconductor substrate. The digital-analog converter is characterized in that the high-order bit constant current source and the end of the semiconductor substrate are arranged so that their distances are substantially equal to each other. 2. The end of the semiconductor substrate is made to have the same distance between the high-order bit constant current source of the digital-analog converter at both ends of the plurality of digital-analog converters and the end of the semiconductor substrate. 2. The digital circuit according to claim 1, wherein a circuit other than the high-order bit constant current source is arranged in a region between the section and the digital-analog converter.
Analog converter. 3. The digital / analog converters at both ends are arranged in the order of the lower bit constant current source and the upper bit constant current source from an end portion on the semiconductor substrate toward a central direction. The digital-analog converter according to claim 1.