JPH0381310B2 - - Google Patents
Info
- Publication number
- JPH0381310B2 JPH0381310B2 JP54042801A JP4280179A JPH0381310B2 JP H0381310 B2 JPH0381310 B2 JP H0381310B2 JP 54042801 A JP54042801 A JP 54042801A JP 4280179 A JP4280179 A JP 4280179A JP H0381310 B2 JPH0381310 B2 JP H0381310B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- resistor
- protection circuit
- width
- silicon resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 30
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 4
- 230000001154 acute effect Effects 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特に絶縁ゲート型
電界効果半導体装置のゲート保護回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a gate protection circuit for an insulated gate field effect semiconductor device.
絶縁ゲート型電界効果素子（以下IGFETと呼
ぶ）における主要な問題の一つとして、高電圧印
加によるゲート絶縁膜破壊がある。これは、構造
上IGFETのゲート絶縁膜が極めて薄く形成され、
さらに絶縁膜が高い抵抗（109〜1019Ω・cm）を
持つているため、静電気等の高電圧がゲート絶縁
膜に印加された場合、絶縁膜は耐圧劣化や破壊を
起こす。 One of the major problems with insulated gate field effect devices (hereinafter referred to as IGFETs) is gate insulating film breakdown due to high voltage application. This is because the gate insulating film of the IGFET is formed extremely thin due to its structure.
Furthermore, since the insulating film has a high resistance (10 9 to 10 19 Ω·cm), when a high voltage such as static electricity is applied to the gate insulating film, the insulating film deteriorates withstand voltage or breaks down.
このような絶縁膜破壊を防止する対策として、
通常入力ゲートに保護回路を接続する方法がとら
れている。 As a measure to prevent such insulation film breakdown,
The usual method is to connect a protection circuit to the input gate.
保護回路としては種々の回路構成が実用されて
おり、多くの保護回路においては、保護回路もし
くはその一部において抵抗が用いられている。こ
の抵抗の効果は高電圧印加時のCR時定数による
遅延や、電圧分割によりゲート絶縁膜への電圧印
加を抑えることにあるが、この抵抗としては拡散
層抵抗もしくは多結晶シリコン抵抗が一般的であ
る。しかしここで問題になるのは、ゲート絶縁膜
保護能力とは、保護回路自身の高電圧に対する強
度も含み、しばしばゲート絶縁膜でなく、保護回
路が破壊することがある。 Various circuit configurations are in practical use as protection circuits, and in many protection circuits, a resistor is used in the protection circuit or a part thereof. The effect of this resistor is to suppress the delay due to the CR time constant when high voltage is applied and the voltage applied to the gate insulating film by voltage division, but this resistor is generally a diffused layer resistor or a polycrystalline silicon resistor. be. However, the problem here is that the ability to protect the gate insulating film also includes the strength of the protection circuit itself against high voltage, and often the protection circuit, not the gate insulating film, is destroyed.
この見地からみると、同一形状とした場合の静
電破壊に対する、保護用抵抗の耐圧は拡散層の方
が多結晶シリコンより高く、抵抗として拡散層を
用いる方がより静電破壊に対して強い保護回路を
作ることができる。これは多結晶シリコン抵抗が
印加された電圧に対して発熱抵抗体となり、ある
一定の電流により溶断するモードを持つている為
で、単結晶の拡散抵抗では見られないものであ
る。 From this point of view, the withstand voltage of a protective resistor against electrostatic damage when the same shape is used is higher for a diffusion layer than for polycrystalline silicon, and using a diffused layer as a resistor is more resistant to electrostatic damage. A protection circuit can be created. This is because the polycrystalline silicon resistor becomes a heat-generating resistor in response to an applied voltage and has a mode in which it melts due to a certain amount of current, something that cannot be seen in single-crystal diffused resistors.
しかしながら、近年多結晶シリコンを抵抗とし
て保護回路を構成することが多くなつてきてお
り、特にMOSメモリー及びCMOS等においては
顕著である。この理由として、拡散層抵抗が基板
との間にＰ−Ｎ接合を形成しており、この接合か
らのキヤリア注入によるメモリー情報の反転や
CMOSラツチアツプ不良の原因となるためであ
る。 However, in recent years, polycrystalline silicon has been increasingly used as a resistor in protection circuits, particularly in MOS memories, CMOS, and the like. The reason for this is that the diffusion layer resistor forms a P-N junction with the substrate, and memory information may be inverted due to carrier injection from this junction.
This is because it causes CMOS latch-up failure.
多結晶シリコン抵抗を使用した保護回路の静電
破壊耐圧は、ほとんどその多結晶シリコン抵抗自
身の耐圧、即ち断面積の電流密度で決定されるの
で、多結晶シリコンの厚さが厚いほど、巾が広い
ほど、又抵抗が高いほど耐圧の高いものとなる。 The electrostatic breakdown voltage of a protection circuit using a polycrystalline silicon resistor is determined mostly by the withstand voltage of the polycrystalline silicon resistor itself, that is, by the current density of its cross-sectional area, so the thicker the polycrystalline silicon, the wider the The wider the resistance and the higher the resistance, the higher the withstand voltage.
一方MOSICにおいては、電気的特性や作製プ
ロセス上の制限から、多結晶シリコンの厚さ、
巾、抵抗値等が決定されるので、これらの定数は
静電耐圧と特性の釣合いのとれた点で決められ
る。さらにこの多結晶シリコンの厚さ、巾、抵抗
値の他に形状によつても耐圧が異なることが明か
らになつた。 On the other hand, in MOSIC, due to electrical characteristics and manufacturing process limitations, the thickness of polycrystalline silicon
Since the width, resistance value, etc. are determined, these constants are determined based on the balance between the electrostatic breakdown voltage and the characteristics. Furthermore, it has become clear that the breakdown voltage varies depending on the shape of the polycrystalline silicon in addition to its thickness, width, and resistance value.
即ち、ICは設計上できるだけ面積を小さくす
ることが必要とされるが、この目的のために多結
晶シリコン抵抗は直線で用いられることは少な
く、曲げて配置されることが多い。 That is, it is necessary to design an IC to make the area as small as possible, but for this purpose, polycrystalline silicon resistors are rarely used in a straight line, but are often arranged in a curved manner.
第１図ａはこの様子を示したものであり、ボン
デイング用金属電極１は接続部２において多結晶
シリコン抵抗直線部３と接続し、この直線部から
多結晶シリコン抵抗屈曲部４を経て他の直線部３
の端部は接続部５において入力保護回路配線金属
と接続されている。このように平面形状が湾曲又
は屈曲している形状のものと、第１図ｂに示すよ
うに平面形状が直線すなわち屈曲部４が存在しな
いものとでは、第１図ｂのように直線状のみの多
結晶シリコンの方が〜50V静電破壊耐圧が高いこ
とがわかり、この原因として湾曲部又は屈曲部に
おいて印加電流の集中により局部加熱が起こり、
この部分での多結晶シリコンの溶断が起こること
が判明した。尚、第１図ｂにおいて第１図ａと同
じ機能の個所は第一の符号で示してある。 Figure 1a shows this situation, where the bonding metal electrode 1 is connected to the polycrystalline silicon resistor straight part 3 at the connection part 2, and from this straight part it passes through the polycrystalline silicon resistor bent part 4 to other wires. Straight section 3
The end portion of is connected to the input protection circuit wiring metal at the connection portion 5. As shown in Fig. 1b, the planar shape is curved or bent, and the planar shape is straight, that is, there is no bent part 4, as shown in Fig. 1b. It was found that polycrystalline silicon has a higher electrostatic breakdown voltage of ~50V, and the cause of this is local heating caused by concentration of applied current at curved or bent parts.
It was found that polycrystalline silicon was fused in this area. In FIG. 1b, parts having the same functions as in FIG. 1a are designated by the first reference numerals.
そこで本発明の目的は、保護回路もしくはその
一部として多結晶シリコン抵抗を用いた場合、そ
の湾曲部もしくは屈曲部の巾を、他の直線部分に
比べて広くすることによつて多結晶シリコン抵抗
の耐圧を集積回路装置の面積を広くすることなく
上げ、MOSICの静電破壊耐圧を上げようとする
ものである。 Therefore, an object of the present invention is to increase the width of the polycrystalline silicon resistor by making the width of the curved part or bent part wider than other straight parts when the polycrystalline silicon resistor is used as a protection circuit or a part thereof. The aim is to increase the withstand voltage of MOSICs without increasing the area of the integrated circuit device, and to increase the electrostatic breakdown voltage of MOSICs.
本発明は、絶縁ゲート型電界効果型半導体装置
の入力ゲート保護回路もしくは入力ゲート保護回
路の一部として多結晶シリコン抵抗を使用してい
る構造において、その多結晶シリコン抵抗の形状
が屈曲もしくは湾曲している部分を、他の直線領
域の巾よりも広くしたことを特徴とする半導体装
置である。 The present invention provides a structure in which a polycrystalline silicon resistor is used as an input gate protection circuit or a part of the input gate protection circuit of an insulated gate field effect semiconductor device, and the shape of the polycrystalline silicon resistor is bent or curved. This semiconductor device is characterized in that the width of the straight line area is made wider than the width of the other straight line area.
以下本発明の実施例を第２図で説明する。尚、
第２図において第１図と同じ機能の個所は同一の
符号で示す。これによれば、多結晶シリコン抵抗
直線部３間の多結晶シリコン抵抗屈曲部７は直線
部より平面形状の巾が広くなつている。 An embodiment of the present invention will be described below with reference to FIG. still,
In FIG. 2, parts having the same functions as in FIG. 1 are designated by the same reference numerals. According to this, the polycrystalline silicon resistor bent portion 7 between the polycrystalline silicon resistor straight portions 3 has a wider planar width than the straight portion.
このように本発明によれば、湾曲部もしくは屈
曲部において多結晶シリコンの巾を広くすること
により、回路のレイアウト変更をすることなく、
静電耐圧を向上させることが可能となる。 As described above, according to the present invention, by increasing the width of the polycrystalline silicon at the curved portion or the bent portion, the circuit layout can be improved without changing the circuit layout.
It becomes possible to improve electrostatic withstand voltage.
第１図ａは従来技術による湾曲又は屈曲してい
る多結晶シリコン抵抗を示す平面図であり、第１
図ｂは従来技術による直線状の多結晶シリコン抵
抗を示す平面図である。第２図は本発明の実施例
を示す平面図である。
尚図において、１……ボンデイング用金属電
極、２……金属電極と多結晶シリコン抵抗との接
続部、３……多結晶シリコン抵抗直線部、４……
多結晶シリコン抵抗屈曲部、５……入力保護回路
金属配線と多結晶シリコン抵抗との接続部、６…
…入力保護回路配線金属、７……多結晶シリコン
抵抗において、直線部より巾を広くした屈曲部で
ある。
FIG. 1a is a plan view showing a curved or bent polycrystalline silicon resistor according to the prior art;
FIG. b is a plan view showing a linear polycrystalline silicon resistor according to the prior art. FIG. 2 is a plan view showing an embodiment of the present invention. In the figure, 1...metal electrode for bonding, 2... connection portion between the metal electrode and polycrystalline silicon resistor, 3... linear portion of polycrystalline silicon resistance, 4...
Polycrystalline silicon resistor bent portion, 5... Connection portion between input protection circuit metal wiring and polycrystalline silicon resistor, 6...
. . . Input protection circuit wiring metal, 7 . . . In a polycrystalline silicon resistor, this is a bent portion that is wider than the straight portion.
Claims (1)
ート保護回路もしくは入力ゲート保護回路の一部
として多結晶シリコン抵抗を使用している構造に
おいて、前記多結晶シリコン抵抗の形状が屈曲も
しくは湾曲している部分の内側および外側をその
近傍に鋭角が形成されないように広げることによ
り、他の直線領域の巾よりも広くしたことを特徴
とする半導体装置。1 In a structure in which a polycrystalline silicon resistor is used as an input gate protection circuit or a part of an input gate protection circuit of an insulated gate field effect semiconductor device, a portion where the shape of the polycrystalline silicon resistor is bent or curved. 1. A semiconductor device characterized in that the width of the linear region is made wider than the width of other linear regions by widening the inner and outer sides of the region so that no acute angles are formed in the vicinity thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4280179A JPS55134976A (en) | 1979-04-09 | 1979-04-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4280179A JPS55134976A (en) | 1979-04-09 | 1979-04-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55134976A JPS55134976A (en) | 1980-10-21 |
| JPH0381310B2 true JPH0381310B2 (en) | 1991-12-27 |
Family
ID=12646062
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4280179A Granted JPS55134976A (en) | 1979-04-09 | 1979-04-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55134976A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01149451A (en) * | 1987-12-04 | 1989-06-12 | Rohm Co Ltd | Protective device for cmos input stage gate |
| JP4646387B2 (en) * | 2000-12-01 | 2011-03-09 | セレック株式会社 | Food storage container |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50134387A (en) * | 1974-04-10 | 1975-10-24 | ||
| JPS5429984A (en) * | 1977-08-10 | 1979-03-06 | Hitachi Ltd | Protector for semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5654603Y2 (en) * | 1973-07-13 | 1981-12-19 |
-
1979
- 1979-04-09 JP JP4280179A patent/JPS55134976A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50134387A (en) * | 1974-04-10 | 1975-10-24 | ||
| JPS5429984A (en) * | 1977-08-10 | 1979-03-06 | Hitachi Ltd | Protector for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55134976A (en) | 1980-10-21 |
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