JP3417646B2 - Layout structure of reference voltage generation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout structure on a semiconductor chip of a reference voltage generating circuit used in, for example, an A / D converter.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of an A / D converter employing a chopper type comparator. For simplicity, a 2-bit A / D converter is shown here. The ladder resistors 11 are connected in series between the high voltage side reference voltage VRT and the low voltage side reference voltage VRB of the A / D converter 10.

The input terminal of each reference voltage VRT, VRB and the connection point between the ladder resistors 11 are connected to the input side of each inverter 14 via each first switch 12 and each hold capacitor 13. Also, this A / D
Each second switch 15 is arranged between the analog input AIN of the converter 10 and each hold capacitor 13. Further, each third switch 16 is arranged between the input and the output of each inverter 14.

The output of each inverter 14 is input to the mismatch detection circuit 17, the output of the mismatch detection circuit 17 is input to the encoder 18, and the encoder 18 outputs the digital output DOUT. In A / D conversion, first, each second switch 15 is turned off, each first switch 12 and each third switch 16 are turned on, and each holding capacitor 13 is supplied with each reference voltage VRT, VRB or ladder. Each reference voltage divided by the resistor 11 is applied, and each hold capacitor 13 is charged to each applied voltage. Thereafter, each first switch 12 and each third switch are turned off and each second switch is turned on, and the analog input AIN is applied to each hold capacitor 13. Then, the logic of the output of each inverter 14 becomes logic “0” or logic “1” depending on whether the voltage of the analog input AIN is higher or lower than the reference voltage applied to each hold capacitor 13 until then. The disagreement detection circuit 17 detects which of the two inverters 14 adjacent to each other causes a logic disagreement (the output of one inverter 14 is a logic “0” and the output of the other inverter 14 is a logic “1”). , That information is transmitted to the encoder 18. In the encoder 18,
Digital output according to the location where the mismatch occurs, that is, digital output DOU according to analog input AIN
T is generated and output.

FIG. 5 is a plan view and a plan view of a layout structure on a semiconductor chip of a reference voltage generating circuit 20 including a portion surrounded by a dotted line in FIG. 4 in the A / D converter 10 shown in FIG. 6 is a sectional view of the semiconductor chip taken along line XX 'in FIG. The polysilicon layer 111 is the insulating film 20.
0 (see FIG. 6) so as to extend vertically in FIG. 5, and the polysilicon layer 111 constitutes the ladder resistor 11 shown in FIG. In addition, in FIG.
On the right side of the polysilicon layer 111, there are two gate electrodes (polysilicon layers) 121 and 1 each extending vertically in the figure.
51, and three diffusion layers 201, 202 and 203, two transistors connected in series are formed. Of this transistor, the gate electrode 121
And the diffusion layers 201 and 202 on both sides thereof form the first switch 12 shown in FIG. Further, the gate electrode 151 and the diffusion layers 202 and 203 on both sides of the gate electrode 151 constitute the second switch 15 although it is not included in the reference voltage generating circuit 20 shown in FIG.

The aluminum wiring 112 has contacts 113,
114 connects the polysilicon layer 111 and the diffusion layer 201. Of the aluminum wiring 112, the uppermost aluminum wiring 112 in FIG. 5 extends beyond the polysilicon layer 111 to the input terminal (not shown) for the reference voltage VRT on the further left side in the drawing. Further, the aluminum wiring 123 having the contact 122 on the gate electrode 121 is a wiring for on / off control of the first switch 12, and the aluminum wiring 153 having the contact 152 on the gate electrode 151.
Is a wiring for on / off control of the second switch 15. The aluminum wiring 205 having the contact 204 in the diffusion layer 202 is a wiring connected to each hold capacitor 13, and the aluminum wiring 207 having the contact 206 in the diffusion layer 203 is a wiring to which the analog input AIN is transmitted. .

[0007]

SUMMARY OF THE INVENTION A having the above configuration
In the / D converter or the reference voltage generating circuit, the reference voltages VRT and VRB are externally supplied. Therefore, when the surge voltage is applied to the input terminal of the reference voltage VRT or the reference voltage VRB, the applied surge voltage is hardly attenuated on the way and the reference voltage VRT shown in the uppermost part of FIG. 5 is input. The diffusion layer 201, which is not shown in FIG. 5, is directly input to the diffusion layer to which the reference voltage VRB is input, and these diffusion layers are easily broken, that is, the electrostatic breakdown voltage is low. There's a problem.

In view of the above-mentioned circumstances, it is an object of the present invention to provide a layout structure of a reference voltage generating circuit which has an improved electrostatic breakdown voltage.

[0009]

A layout structure of a reference voltage generating circuit of the present invention which achieves the above object is a ladder resistor arranged between two reference potentials, these two reference potentials and these two reference potentials. 1 of ladder resistance between potentials
In a layout structure of a reference voltage generation circuit including a plurality of transistors each having a drain connected to one or a plurality of nodes, ladder resistances are sequentially connected through contacts with a metal wiring layer. It is characterized in that it has a divided polysilicon layer, and that the drain has a diffusion layer that extends between the polysilicon layers.

Here, the diffusion layer preferably extends so as to surround at least a part of the polysilicon layer.

[0011]

In the layout structure of the reference voltage generating circuit according to the present invention, the polysilicon layer forming the ladder resistance is divided into a plurality of layers, and the diffusion layer 201 shown in FIG. 5 is inserted into the divided polysilicon layers. Since it spreads, a large junction capacitance is formed there, and the electrostatic breakdown resistance is improved.

In this case, if the diffusion layer is formed so as to surround the polysilicon layer forming the ladder resistance, the junction capacitance of the diffusion layer is further increased and the electrostatic breakdown resistance is further improved. Further, if the resistance value of the ladder resistor is small, there is a problem that a large current flows through the ladder resistor and noise becomes large. Conversely, if the resistance value of the ladder resistor is large, the time constant for charging the hold capacitor 13 becomes large. There is a problem that the / D conversion speed is lowered, and the resistance value is selected in consideration of the balance thereof. However, when the structure in which the diffusion layer is widened is adopted as in the present invention, the increase of the junction capacitance serves as a filter. In addition, the heat dissipation characteristics are improved due to the large junction area, and the noise is reduced as a synergistic effect of them.

Further, in the layout structure shown in FIG. 5, there is a space between the ladder resistor (polysilicon layer 111) and the diffusion layer 201, which causes a waste of space. Since the diffusion layer is inserted between the divided polysilicon layers or the diffusion layers surround the polysilicon layers, there is no useless space as shown in FIG. 5, and the area can be reduced. It will also be connected.

[0014]

EXAMPLES Examples of the present invention will be described below. 1 is a plan view showing an embodiment of a layout structure of a reference voltage generating circuit of the present invention, FIG. 2 is a sectional view taken along line XX 'of FIG.
FIG. 3 is a sectional view taken along the line YY 'of FIG. The elements corresponding to the elements of the conventional example shown in FIGS. 5 and 6 are denoted by the same numbers as those shown in FIGS. 5 and 6 over the difference in layout, and the differences will be described.

In the layout structure shown in FIGS. 1 to 3, the polysilicon layer 1 constituting the ladder resistor 11 (see FIG. 4) is used.
11 is divided into a plurality of parts, and the plurality of polysilicon layers 111 are formed by aluminum wirings 112 and contacts 113.
They are connected. Further, the diffusion layer 201 extends even between the plurality of polysilicon layers 111, and further extends so as to surround each diffusion layer 201. Therefore, a large junction capacitance C is formed as shown in FIG. Further, in this embodiment, as shown in FIG. 3, the polysilicon layer 111 faces the substrate with a thin oxide film interposed therebetween, and a considerably large MOS capacitance C ′ is also formed therein. Therefore, the surge voltage input via the aluminum wiring 112 is attenuated by those capacitances,
Therefore, the electrostatic breakdown voltage is improved.

Further, the diffusion layer 201 is the polysilicon layer 11
Since it is widely spread around 1, the heat dissipation is improved in addition to the increase in the capacitance thereof, the thermal noise of the polysilicon layer 111 (ladder resistor 11) is suppressed, and a highly accurate reference voltage can be generated. it can. Furthermore, FIGS.
In the embodiment shown in FIG. 5, there is no wasted space between the polysilicon layer 111 and the diffusion layer 201 in the layout structure shown in FIG. 5, which contributes to high integration.

In the above embodiment, the diffusion layer 201 is formed so as to completely surround the polysilicon layer 111, but it is not always necessary to surround the entire circumference, and the polysilicon layer 111 is not necessarily surrounded by the polysilicon layer 111. It may be extended up to, and the layout is performed according to the design value of the electrostatic breakdown voltage.

[0018]

As described above, according to the present invention,
A reference voltage generation circuit having an improved electrostatic breakdown voltage is configured.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a layout structure of a reference voltage generating circuit of the present invention.

FIG. 2 is a sectional view taken along line XX ′ of FIG.

FIG. 3 is a cross-sectional view taken along the line YY ′ of FIG.

FIG. 4 is a configuration diagram of an A / D converter that employs a checker type comparator.

FIG. 5 is a plan view of a layout structure of a reference voltage generating circuit on a semiconductor chip.

FIG. 6 is a sectional view of the semiconductor chip taken along line XX ′ in FIG.

[Explanation of symbols]

111 polysilicon layer (ladder resistance) 112, 123, 153, 205, 207 aluminum wiring 113, 114, 122, 152, 204, 206 contact 121, 151 gate electrode 201, 202, 203 diffusion layer

Continuation of the front page (56) References JP-A-62-172750 (JP, A) Actual development 1-108616 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21 / 822 H01L 27/04 H01L 27/06

Claims (2)

(57) [Claims] 1. A ladder resistor arranged between two reference potentials, and a drain connected to each of the two reference potentials and one or more nodes of the ladder resistor between the two reference potentials. In the layout structure of the reference voltage generating circuit including a plurality of transistors, the ladder resistor has a plurality of divided polysilicon layers that are sequentially connected via a contact with a metal wiring layer, and A layout structure of a reference voltage generating circuit, wherein the drain has a diffusion layer extending between the polysilicon layers. 2. The layout structure of the reference voltage generating circuit according to claim 1, wherein the diffusion layer is spread so as to surround at least a part of the polysilicon layer.