JP2967265B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ladder resistance circuit comprising a multi-layer polycrystalline silicon film and a semiconductor device comprising the ladder resistance and a transistor.

[0002]

2. Description of the Related Art FIG. 2 is a sectional view of a resistance element used in a conventional ladder resistance circuit and an insulated gate field effect transistor (hereinafter abbreviated as MISFET). A polycrystalline silicon film is provided on a surface of a substrate 1 with an oxide film 2 interposed therebetween. The polycrystalline silicon film includes a gate electrode of a MISFET including a gate oxide film 3 in which a part of the oxide film 2 is thinned, a source / drain region 4, and a gate electrode 5.
And a resistance element. A high-concentration impurity region 6 is formed on both sides of the resistance element made of a polycrystalline silicon film, and a low-concentration impurity region 7 for determining the resistance value of the resistance element is formed therebetween. A metal wiring 9 is provided on the high-concentration impurity region 6 of the resistance element via a contact hole of the intermediate insulating film 8 to maintain ohmic contact with the high-concentration impurity region. Further, a silicon nitride film passivation 10 is provided on the entire surface.
The ladder resistance circuit is formed on the same substrate surface by connecting a plurality of resistance elements of FIG. 2 in series or in parallel via metal wiring.

[0003]

However, there have been the following problems when integrating an insulated gate field effect transistor and a ladder resistance circuit. When the resistance value of the resistance element made of polycrystalline silicon is designed to be large, it is necessary to lengthen the resistance proportionately. However, the chip size becomes large, so that an inexpensive circuit cannot be supplied. Especially,
In D / A converters and A / D converters, in which the area and accuracy of the ladder resistance circuit greatly affect product cost and product performance, the gate electrode of an insulated gate field effect transistor and a thin film of ladder resistance provided on the same substrate If the ladder resistance is also formed, the area of the ladder resistor increases, and the cost also increases.

Accordingly, an object of the present invention is to solve the above-described conventional problems by increasing the resistance value per unit area of a ladder resistance circuit in a semiconductor device in which transistors are simultaneously integrated and a chip associated therewith. The goal is to reduce the size, lower the cost, and increase the accuracy.

[0005]

In order to solve the above problems, the present invention comprises a reference voltage means, a voltage amplifying means, a voltage dividing means and a digital signal processing means, wherein the voltage amplifying means comprises at least a ground voltage and a digital signal. A voltage selected from the voltage of the signal processing means is input, a signal obtained by amplifying the voltage of the digital signal processing means is output, the voltage dividing means is constituted by a ladder resistance circuit, and the ladder circuit is configured to output the voltage outputted from the reference voltage means. A semiconductor device which divides and outputs a plurality of currents having different values to the digital voltage signal processing means; and a reference voltage means, a voltage comparison means, a voltage division means and an encoder, wherein the voltage comparison means has at least an input. A voltage selected from the voltage and the voltage of the voltage dividing means is input, and a signal corresponding to the two voltage differences is output to the encoder. A signal from a stage is input, a signal from a plurality of voltage comparing means is compared, a plurality of voltages are output, and a voltage dividing means is constituted by a ladder resistance circuit, and a voltage outputted from a reference voltage means is divided. In the semiconductor device, a ladder resistance circuit includes a first resistor made of a first polycrystalline silicon film provided on a substrate surface, and a second resistor provided via the first resistor and an interlayer insulating film. And a second resistor made of a polycrystalline silicon film.

Alternatively, the semiconductor device includes a first polycrystalline silicon film, an interlayer insulating film, a second polycrystalline silicon film, and an insulated gate field effect transistor, and has a thickness of 2,000 to 400.
At 0 °, a first polycrystalline silicon film having an impurity concentration of 10 ²⁰ atoms / cm ³ or more forms a gate electrode of an insulated gate field effect transistor, and a second polycrystalline silicon film forms a ladder resistance circuit. Semiconductor device.

Further, a semiconductor device is characterized in that the second polycrystalline silicon is thinner than the first polycrystalline silicon film. Further, the thickness of the second polycrystalline silicon is 100
From 1000 ° to 1 × 10 ¹⁵ to 5 × 10
^The semiconductor device was characterized by being ¹⁹ atoms / cm ³ .

In addition, a semiconductor device is characterized in that the thickness of the second polycrystalline silicon is 500 °. Further, the interlayer insulating film is formed of NS having a thickness of 1000 to 4000 mm.
The semiconductor device was a G film.

Alternatively, the interlayer insulating film has a thickness of 200 to 700 °.
A semiconductor device characterized in that it is a thermal oxide film having a thickness of

[0010]

Since the ladder resistance circuit is formed of a polycrystalline silicon film having a multilayer structure, there is no need to provide a resistance interval between the ladder resistance circuits and the area can be reduced. Further, since the gate electrode of the insulated gate transistor is formed of the first layer of polycrystalline silicon and the ladder resistance circuit is formed of the second layer of polycrystalline silicon, the polycrystalline silicon constituting the ladder resistance circuit is formed. The thickness of crystalline silicon, heat treatment, impurity implantation conditions, etc.
It can be set freely without being restricted by the thickness of polycrystalline silicon constituting the gate electrode of the SFET, heat treatment, impurity implantation conditions, and the like.

Further, since the ladder resistance circuit is formed of a thin polycrystalline silicon film, it is higher when impurities of the same concentration are implanted than in the case where the ladder resistance circuit is formed of a thick polycrystalline silicon film. A resistance value can be obtained.
Therefore, the length of the resistance of the ladder resistance circuit can be reduced, and the area required for the ladder resistance circuit can be reduced.

Further, when the thickness of the second polycrystalline silicon is 10
0 to 1000 ° and impurity concentration of 1 × 10 ¹⁵ to 5 × 1
By setting the value to 0 ¹⁹ atoms / cm ³ , the resistance value of the resistance element forming the ladder resistance circuit can be stably obtained, and the variation in the resistance value due to the variation in the impurity concentration can be suppressed.

Further, the interlayer insulating film has a thickness of 1000 to 4000.
With the NSG film having the thickness of Å, it is possible to prevent contact etching failure and leakage due to pinholes in the NSG film. Alternatively, the interlayer insulating film has a thickness of 200 to 700 °.
By using a thermal oxide film having a thickness of 2 mm, it is possible to avoid leakage between the first and second layers of polycrystalline silicon and increase in energy of ion implantation performed through this thermal oxide film.

[0014]

FIG. 1 is a cross-sectional view of a MISFET and a resistor constituting a semiconductor device according to the present invention. An oxide film 2 is provided on the surface of a substrate 1. On oxide film 2, a first polycrystalline silicon film is provided. This first polycrystalline silicon film has a low pressure CV of 500 to 700 ° C.
D and is mainly used as a gate electrode of a MISFET. Therefore, the first polycrystalline silicon film generally has a thickness of 2000 to 4000 °, an impurity concentration of 10 ²⁰ atoms / cm ³ or more, and a sheet resistance of 10
0 Ω / □ or less. An interlayer insulating film 11 is provided on the first polycrystalline silicon film, and a second polycrystalline silicon film is provided on the interlayer insulating film. This interlayer insulating film is provided with NSG (Non-doped Silicate).
(Glass) film or thermal oxide film. In the case of NSG, contact etching failure and NS
In order to prevent leakage due to pinholes in the G film, the film thickness is selected between 1000 and 4000 °. In the case of a thermal oxide film, leakage between the first and second layers of polycrystalline silicon,
In order to avoid high energy of ion implantation performed through the thermal oxide film, a film thickness of 200 to 700 ° is selected.

The second polycrystalline silicon is 500 to 700
Film formed by low pressure CVD at ℃ and the film below by ion implantation
50 to prevent penetration and poor coverage.
Choose a film thickness value between 0 and 2000 °. This second polycrystalline silicon
The silicon film includes a low concentration impurity region 7 and a high concentration impurity region.
6, mainly consisting of high-resistance ladder resistor circuits.
Of the low-concentration impurity region used for the
On the other side, there is a high concentration
It is composed of a resistance element provided with a pure region. This low concentration
The impurity concentration in the impurity region has a stable value as a resistance element.
10 to get ^Fifteen~ 5 × 10¹⁹atoms / cm^ThreeTo the value of
Choose. The optimal value is 10¹⁷~ 5 × 10 ¹⁹atoms /
cm^ThreeIs preferred.

An intermediate insulating film 8 is formed on the second polycrystalline silicon film. A contact hole is provided in the intermediate insulating film on the high-concentration impurity region on the second polycrystalline silicon film, and the metal electrode 9 is electrically connected to each high-concentration impurity region via the contact hole. Is provided. Generally, an aluminum electrode is used as such a metal electrode. A silicon nitride film passivation 10 is provided on the metal electrode 9.

The thickness of the second polycrystalline silicon film is 5 as described above.
Since it can be set arbitrarily between 00 and 2000 °, for example, 1000 ° thinner than the first polycrystalline silicon can be selected. In this case, in order to obtain the same resistance value as that of the first polycrystalline silicon resistor, the impurity to be doped into the second polycrystalline silicon is made higher in concentration than in the case where the resistance is formed by the first polycrystalline silicon. be able to. When the concentration of the polycrystalline silicon low-concentration region that determines the resistance value of the polycrystalline silicon resistor increases, the rate at which the implanted impurities segregate at the grain boundaries can be reduced, so that the variation in the resistance value caused by the impurity segregation variation is reduced. be able to. Therefore, in order to manufacture a highly accurate ladder resistance circuit, it is desirable to reduce the thickness of the polycrystalline silicon constituting the resistance element.

Such a structure can be applied to various semiconductor integrated circuits that require a MISFET and a high-precision ladder resistance circuit. As an example, FIG. 3 shows a circuit block diagram of a current comparison type D / A converter. A D / A converter is a semiconductor device that converts a binary digital voltage signal into a decimal analog voltage signal. FIG. 3 shows an example of a circuit that realizes conversion of a voltage signal due to a difference in the amount of current flowing through the circuit. It is. This D / A converter is provided with reference voltage means 9.
01, digital voltage signal processing means 905, voltage amplifying means 906, and a plurality of resistors R301 as voltage dividing means.
A ladder resistance circuit composed of R302 outputs an analog voltage signal from an output terminal F.

The reference voltage means 901 is connected between the power supply line 88 and the ground line 89 and applies a constant voltage to the connection point Q.
It has the function to output to. Digital voltage signal processing means 90
5 processes the input binary digital voltage signal, and switches S101 to S104 corresponding to each bit of the binary number.
To the connection point U side or the ground terminal H side. Then, a constant current corresponding to the digital voltage signal is output to the connection point U. This example corresponds to a 4-bit digital voltage signal. For example, when the digital voltage signal is 1010, S101 and S103 are switched to the connection point U side, and S102 and S104 are switched to the ground terminal H side.

The voltage amplification means 906 has a voltage amplification degree of 100
More than twice, it has two input terminals and has the function of amplifying the difference between the voltages applied to the two input terminals and outputting it to the output terminal. In this example, by connecting the non-inverting terminal 114 of the voltage amplifying means to the ground line 89 and connecting the inverting terminal 113 to the connection point V and the output terminal F via R301, the digital voltage signal processing means 905 The output constant current is converted to an output voltage. This voltage amplifying means 9
06 has a high voltage amplification factor of 100 times or more, so the potentials of the connection points U and V are stable at 0 V, which is the same as the ground line.

Each resistor R301 constituting the ladder resistor circuit,
Assuming that each resistance value of R302 is R301 and R302,
Select a value that satisfies the following relationship. R302 = 2 × R301 As described above, since the potential of the connection point U is the same 0 V as the ground terminal H, the switches S101 to S104 in the digital voltage signal processing means are connected to the connection point U side or the ground terminal H. No matter which side is switched, the potential on the digital voltage signal processing side becomes 0 V with respect to R302. From the above conditions, the lower equivalent resistance value is equal to R302 (= 2 × R301) from any connection point of Q, R, S, and T. Therefore, assuming that the current flowing from the reference voltage means to the connection point Q is IR, the current flowing from the switch S101 to S104 is IR / 2, IR / 4, IR / 8 and IR / 16, respectively.
This current ratio corresponds to the ratio when each binary bit is converted to a decimal number.

The constant voltage output from the reference voltage means 901 is VR, the output voltage from the output terminal F is VO, and the switch S
Each bit corresponding to 101 to S104 is represented by B1, B2, B
3, B4 (where B1 to B4 are 1 or 0, and this combination represents a digital voltage signal), the analog output voltage V0 is as follows.

V0 =-｛(1/2) × B1 + (1/4) × B2 + (1 /
8) × B3 + (1/16) × B4｝ VR R301 and R302, which are components of the ladder resistance circuit in the D / A converter, are made of polycrystalline silicon resistors.
Since the constants such as 、 and の in the above equation are based on the ratio of the resistances of R301 and R302, that is, R302 = 2 × R301, this is determined by the ratio of the polycrystalline silicon resistance. Therefore, the accuracy of the resistance ratio affects the accuracy of the D / A converter.

In the ladder resistance circuit of FIG. 3, if the number of bits of the digital signal to be converted increases by one, the number of pairs of resistors R301 and R302 connected in parallel increases by one. That is, if the number of bits of the digital signal is increased in order to increase the resolution of the signal, the area required for the ladder resistance circuit increases. However, the ladder resistance circuit can be accurately formed in a small area by forming the polycrystalline silicon resistor with the second polycrystalline silicon film as described later.

This method can be applied to all D / A converter circuits having a ladder resistance circuit composed of polycrystalline silicon resistance. FIG. 4 shows the A / D of the parallel comparison system according to the present invention.
It is a circuit block diagram in the case of applying to a converter. A
The / D converter is a semiconductor device that converts an analog voltage signal into a binary digital voltage signal. FIG. 4 compares an analog input voltage with various constant voltages to determine a constant voltage closest to the analog input voltage. Is a circuit that selects and converts it into a binary digital voltage.

This A / D converter is provided with a reference voltage means 9.
01 and a plurality of resistors R303 and R3 as voltage dividing means.
04, a ladder resistance circuit 907, a plurality of voltage comparison means 903, and an encoder 908. The analog voltage signal input from the analog input voltage signal input terminal W is converted into a binary digital voltage signal. It has a function of outputting from a digital voltage signal output terminal X. FIG.
For example, it corresponds to a 3-bit digital voltage signal.

The reference voltage means 901 is connected between the power supply line 88 and the ground line 89 and has a function of outputting a constant voltage to the ladder resistance circuit 907. Here, it is assumed that the constant voltage output from the reference voltage means is higher than the voltage input from the analog voltage signal input terminal.

The ladder resistance circuit 907 includes a plurality of resistors R3
03, R304, and has a function of dividing the constant voltage output from the reference voltage means into a plurality of voltages, and outputting the plurality of voltages to the plurality of voltage comparison means 903, respectively. The voltage comparison unit 903 has a function of comparing an analog voltage signal from the analog voltage signal input terminal W with a voltage from the ladder resistance circuit 907 and outputting a different voltage depending on the magnitude.

The encoder 908 is constituted by a plurality of logic circuits such as a logical sum gate circuit, receives a set of voltages output from a plurality of voltage comparing means as inputs, compares and determines the plurality of voltages, and determines a binary digital number. It has a function of converting a voltage signal to a digital voltage signal output terminal X.

The constant voltage output from the reference voltage is divided by the resistance ratio of the ladder resistance circuit such as R303 and R304. In this example, five voltages are divided into connection points Y, Z, and A.
A, BB and CC. Each of the plurality of voltages is compared with an analog voltage input signal by voltage comparison means,
If the analog voltage input signal is larger, the power supply voltage is used. If the analog voltage input signal is smaller, the ground voltage (0 V) is used.
Is output from the voltage comparison means to the encoder. That is, for example, if the voltage value of the analog voltage input signal is a value between the voltage value of the connection point Z and the voltage value of the connection point AA, if the power supply voltage is 1 and the ground voltage is 0, the output from the voltage comparison means Are respectively 00011 from the top. This signal is
The analog voltage input signal is a value approximating the analog voltage input signal. By converting the signal with an encoder, a digital voltage signal representing the analog voltage input signal in a binary number is obtained from an output terminal.

Here, the components of the ladder resistance circuit in the A / D converter, R301 and R302, are made of polycrystalline silicon resistors. Therefore, the precision of the resistance ratio of the polycrystalline silicon depends on the digital voltage output signal. Accuracy will be affected. The ladder resistance circuit can be accurately formed with a small area by forming the polycrystalline silicon resistor with the second polycrystalline silicon film as described later. Further, this method can be applied to all A / D converter circuits having a ladder resistance circuit constituted by a polycrystalline silicon resistor.

As described above, the A / D converter and the D /
Most A converters use a ladder resistor circuit composed of a resistive element composed of a polycrystalline silicon film to divide a voltage or divide a current. A / D converter and D /
This has a great effect on the conversion accuracy of the A-converter. In general, if the number of digital bits for conversion is large, extra resistive elements corresponding to the number of added bits must be formed.Therefore, the higher the resolution of the digital signal, the larger the ladder resistor circuit is required. This leads to an increase in cost based on an increase in chip area. In other words, high precision and area reduction of the ladder resistance circuit are very large factors that affect the accuracy and cost of A / D converters and D / A converters as products.

Incidentally, all the resistance elements in the ladder resistance circuit used in the D / A converter and the A / D converter described in FIGS. 3 and 4 have the minimum resistance of a certain polycrystalline silicon film as shown in FIG. It is formed by serial or parallel body. This minimum resistor is a resistor having a minimum width and length within a range where resistance value variation does not increase.A ladder resistor circuit is formed by electrically connecting a plurality of such minimum resistors at the same interval with metal wiring or the like. Connect to and configure. On both sides of each minimum resistor, a high concentration impurity region 6 is provided in order to obtain an ohmic contact with a metal wiring. A low-concentration impurity region 7 is formed between the high-concentration impurity regions, and the resistance value of the resistance element is determined by the impurity concentration in this region, the thickness of the polycrystalline silicon film, and the width and length of the minimum resistor. That is, if the width and length of the minimum resistor can be reduced without impairing the resistance value and the resistance value variation of the minimum resistor, the area of the ladder resistance circuit can be reduced.

FIG. 6 shows the dependence of the sheet resistance of the polycrystalline silicon on the concentration of the low concentration impurity region which determines the resistance value of the polycrystalline silicon resistance, using the polycrystalline silicon film thickness as a parameter. When the concentration of the low-concentration impurity region of the polycrystalline silicon resistor is reduced, the variation in the resistance value of the polycrystalline silicon resistor increases due to characteristics of the polycrystalline silicon, such as the segregation of the implanted impurities at the grain boundaries. However, in order to obtain the same resistance value, it is possible to increase the concentration of the low-concentration impurity region by reducing the thickness of the polycrystalline silicon as compared with the case where the thickness is large, as much as the resistance value can be increased by thinning. The influence of segregation variation of impurities is reduced. Therefore, when forming resistive elements having the same resistance value, a thinner polycrystalline silicon film is more advantageous against resistance value variation due to impurity concentration.

FIG. 7 shows the in-plane variation of the polycrystalline silicon film thickness with respect to the polycrystalline silicon film thickness. As shown in the figure, when the polycrystalline silicon film thickness becomes thinner than 500 °,
Variations in the thickness of the polycrystalline silicon within the substrate surface cannot be ignored. Therefore, in this region, the resistance value variation of the resistance element formed of the polycrystalline silicon film is affected by the film thickness variation. Therefore, it is preferable that the thickness of the thin film for reducing the resistance value variation of the resistive element be at least 500 °.

FIG. 8 shows the dependence of the resistance value variation on the sheet resistance of the resistance element made of the polycrystalline silicon film, using the polycrystalline silicon film thickness as a parameter. FIG.
7 shows that when the film thickness is 500 ° or more, the thinner the film thickness, the smaller the variation in the resistance value.

FIG. 9 shows another factor of the variation in the resistance value of the polycrystalline silicon resistance, which is the length of the resistance element.
The dependence of the variation in the resistance value is shown using the thickness of the polycrystalline silicon film as a parameter. As shown in this figure, when the length of the polycrystalline silicon resistor is reduced, the resistance value variation generally increases. A similar phenomenon occurs even if the thickness of the polycrystalline silicon is reduced. However, as described above, when the thickness is reduced, variation in resistance segregation is small because variation in impurity segregation is small. The increase in the variation in the resistance value due to the reduction in the length of the polycrystalline silicon resistor is caused by the variation in the diffusion of the impurity in the high-concentration impurity region, which diffuses into the low-concentration impurity region of the resistance element. Since the polycrystalline silicon film has a grain boundary with low crystallinity, impurities are easily diffused in this portion, and at the same time, the diffusion length tends to vary. Therefore, when the length of the polycrystalline silicon resistor is shortened, the rate at which the variation in the diffusion length affects the entire resistance value increases, and the variation in the resistance value increases.

The length of the minimum resistor described above is selected based on the tendency of the resistance value variation. For example, when the thickness of the polycrystalline silicon is 3500 ° in FIG. 9, if the length of the polycrystalline silicon resistor is 100 μm or more, a polycrystalline silicon resistor having a small resistance variation can be obtained. However, when the polycrystalline silicon film thickness is set to 1000 °, it is understood that 50 μm or more is sufficient to suppress the same resistance value variation. Accordingly, the length of the minimum resistor is set to 3500 °
Is 100 μm, the thickness may be 50 μm when the film thickness is 1000 °. In other words, by reducing the thickness of the polycrystalline silicon film, the resistance length can be reduced without impairing the resistance value and the resistance variation of the resistance element. Therefore, the area of the ladder resistance circuit using this resistance element can be reduced.

Conversely, if the ladder resistance circuit has the same area, a highly accurate ladder resistance circuit with less resistance value variation can be formed by thinning the polycrystalline silicon film. Therefore, by using this ladder resistance circuit for the D / A converter and the A / D converter, the accuracy of the current division or the voltage division described above is improved,
A D / A converter and an A / D converter with high conversion accuracy can be obtained. For a D / A converter and an A / D converter that compensate for a certain conversion accuracy, the conversion accuracy is improved by using a thin polycrystalline silicon film as in the method of the present invention. This has the advantage of increasing the product yield.

[0040]

According to the present invention, a ladder resistor having a large resistance value can be realized in a small area. Further, the gate electrode of the MISFET provided on the same substrate can be easily formed by the same process.

[Brief description of the drawings]

FIG. 1 is a sectional view of a MISFET and a resistance element according to the present invention.

FIG. 2 is a cross-sectional view of a conventional MISFET and a resistance element.

FIG. 3 is a circuit diagram of a D / A converter according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of an embodiment of the A / D converter of the present invention.

FIG. 5 is a plan view of the resistance element of the present invention.

FIG. 6 is a graph showing the relationship between the polycrystalline silicon low-concentration impurity concentration and the polycrystalline silicon sheet resistance of the resistive element of the present invention.

FIG. 7 is a graph showing the relationship between the polycrystalline silicon film thickness and the in-plane variation of the polycrystalline silicon film thickness of the resistive element of the present invention.

FIG. 8 is a graph showing a relationship between a polycrystalline silicon sheet resistance and a variation in adjacent polycrystalline silicon resistance values of the resistance element of the present invention.

FIG. 9 is a graph showing the relationship between the minimum resistance length and the variation in adjacent polycrystalline silicon resistance value of the resistance element of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Oxide film 3 Gate oxide film 4 Source / drain region 5 Gate electrode 6 High concentration impurity region 7 Low concentration impurity region 8 Intermediate insulating film 9 Metal wiring 10 Silicon nitride film passivation 11 Interlayer insulating film 12 Contact hole 88 Power supply line 89 Ground line 93 Output terminal F 94 Power supply terminal G 95 Ground terminal H 901 Reference voltage means 903 Voltage comparison means 905 Digital voltage signal processing means 906 Voltage amplification means 907 Ladder resistance circuit 908 Encoder 107 Connection point Q 108 Connection point R 109 Connection point S 110 Connection point T 111 Connection point U 112 Connection point V 113 Inverting terminal 114 Non-inverting terminal 115 Analog voltage signal input terminal W 116 Digital voltage signal output terminal X 117 Connection point Y 118 Connection point Z 119 Connection point AA 120 Connection point BB 21 connection point CC

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-316467 (JP, A) JP-A-2-79470 (JP, A) JP-A-63-207165 (JP, A) JP-A-4- 40707 (JP, A) JP-A-8-213912 (JP, A) JP-A-62-45162 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/04 H01L 21 / 822

Claims (9)

(57) [Claims] 1. An insulated gate field effect transistor
Reference voltage means and the voltage amplifier means and the digital signal processing hand made
Has a stage, a voltage dividing means including a ladder resistor circuit, said voltage amplification means receives the voltage selected from a voltage of at least a ground voltage the digital signal processing means to amplify the voltage of the digital signal processing means outputs a signal, the voltage dividing means divides a voltage output from the reference voltage unit, and outputs a current of a plurality of different values in the digital voltage signal processing means, and the reference voltage means and said voltage amplification means The digital signal
Insulated gate field effect transistor constituting the signal processing means
Gate electrode is provided on the semiconductor substrate via an insulating film.
And the thickness is 2000-4000mm,
First polycrystal having a substance concentration of 10 ²⁰ atoms / cm ³ or more
A ladder resistance circuit, comprising a first polycrystalline silicon film;
Second polycrystalline silicon film provided via an interlayer insulating film
It is made of, and wherein a. 2. An insulated gate field effect transistor
A reference voltage means and the voltage comparing means and the encoder comprising, Rada
Has a voltage dividing means consisting of over resistor circuit, said voltage comparator means receives a voltage selected from a voltage of at least the input voltage the voltage dividing means, outputting a signal corresponding to the two voltage differences to the encoder and, the encoder inputs the signals from the plurality of voltage comparing means compares the signals from the plurality of voltage comparing means outputs a plurality of voltages, said voltage dividing means prior Symbol reference voltage means dividing the voltage output from the said reference voltage means and the voltage comparing means encoder
The gate of the insulated gate field effect transistor
When the electrodes are provided on a semiconductor substrate via an insulating film,
It has a thickness of 2000-4000 mm and an impurity concentration of 1
The first polycrystalline silicon film of 0 ²⁰ atoms / cm ³ or more
From it, the ladder resistor circuit, said first polycrystalline silicon film
Second polycrystalline silicon film provided via an interlayer insulating film
It is made of, and wherein a. 3. The method according to claim 1, wherein said second polycrystalline silicon film is formed of said first polycrystalline silicon film.
2. The thin film according to claim 1, wherein said thin film is thinner than said polycrystalline silicon film.
Or the semiconductor device according to 2 . 4. The method according to claim 1, wherein said second polycrystalline silicon film has a thickness of 1
2. The method according to claim 1, wherein
3. The semiconductor device according to 2 . 5. A serial <br/> mounting semiconductor device to claim 1 or 2, wherein the thickness of the second polycrystalline silicon film is about 500 Å. 6. The semiconductor device according to claim 1 or 2 average grain size of the second polycrystalline silicon film is characterized in that it is a 200～1000A. 7. An impurity concentration of said second polycrystalline silicon film.
Degrees from the ^{1 × 10 15 5 × 10 19} atoms / cm 3 der
The semiconductor device according to claim 4, wherein: 8. The method according to claim 1, wherein the interlayer insulating film has a thickness of 1,000 to 4,000.
Ｇ NSG (Nondoped Silicat)
claim, characterized in that a e Glass) film 1 or
3. The semiconductor device according to item 2 . 9. The method of claim 1, wherein the interlayer insulating film is a thickness of the thermal oxide film of 700Å from 200 or
3. The semiconductor device according to 2 .