JP2624280B2 - IIL element - Google Patents
IIL elementInfo
- Publication number
- JP2624280B2 JP2624280B2 JP63016083A JP1608388A JP2624280B2 JP 2624280 B2 JP2624280 B2 JP 2624280B2 JP 63016083 A JP63016083 A JP 63016083A JP 1608388 A JP1608388 A JP 1608388A JP 2624280 B2 JP2624280 B2 JP 2624280B2
- Authority
- JP
- Japan
- Prior art keywords
- iil
- wiring
- gnd
- gate
- gates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明はIIL素子を用いた。IC,LSIにおける接地（以
下GNDとも称する。）用金属配線に関する。DETAILED DESCRIPTION OF THE INVENTION INDUSTRIAL APPLICATION The present invention uses an IIL device. It relates to a metal wiring for grounding (hereinafter also referred to as GND) in ICs and LSIs.
従来の技術 半導体チップ上に形成される複数のIIL素子のインジ
ェクターGND間電位差（PNPトランジスタのベース・エミ
ッタ間電位差）の半導体チップ上でのばらつきを低減す
るために、第４図に示す構造が知られている。2. Description of the Related Art The structure shown in FIG. 4 is known to reduce the variation on the semiconductor chip of the potential difference between the injector and GND (potential difference between the base and emitter of a PNP transistor) of a plurality of IIL elements formed on the semiconductor chip. Have been.
同図においては、複数のIIL素子21のインジェクタに
接続し、半導体基板表面上に延びているアルミニウム配
線22と半導体基板に接続するアルミニウム配線24とを設
け、上記配線22はインジェクタ電流供給端子23に接続
し、上記配線24はGND端子25に接続している。同図より
明らかなように、配線22と24とは互いに平行の配置で、
インジェクタ端子23とGND端子25とは互いに対向する方
向に設けられている。上記アルミニウム配線22にはそれ
ぞれのIIL素子21に供給する電流が流れるが、この場
合、端子23に近いほど電流が大きい。アルミニウム配線
22における抵抗により、この配線22上の電位は第５図曲
線ａのように低下する。逆にアルミニウム配線24上にお
ける電位は第５図曲線ｂのように上昇する。第４図で
は、各IILゲート21のインジェクターGND間の電位差のば
らつきが端子23と25の配置によって、配線22の電圧降下
とGND配線24のGND電位の上昇を利用できるようになるの
で減少する。第１図の配線領域は複数のIILゲートから
なる群を複数個（この場合は２個）配置した構造であ
る。In the figure, an aluminum wiring 22 connected to the injectors of the plurality of IIL elements 21 and extending on the surface of the semiconductor substrate and an aluminum wiring 24 connected to the semiconductor substrate are provided, and the wiring 22 is connected to the injector current supply terminal 23. The wiring 24 is connected to the GND terminal 25. As is clear from the figure, the wirings 22 and 24 are arranged in parallel with each other,
The injector terminal 23 and the GND terminal 25 are provided in directions facing each other. A current supplied to each of the IIL elements 21 flows through the aluminum wiring 22. In this case, the current increases as the distance from the terminal 23 increases. Aluminum wiring
Due to the resistance at 22, the potential on the wiring 22 decreases as shown by the curve a in FIG. Conversely, the potential on the aluminum wiring 24 rises as shown by the curve b in FIG. In FIG. 4, the variation in the potential difference between the injector GND of each IIL gate 21 is reduced because the arrangement of the terminals 23 and 25 makes it possible to utilize the voltage drop of the wiring 22 and the rise of the GND potential of the GND wiring 24. The wiring region in FIG. 1 has a structure in which a plurality of groups (two in this case) composed of a plurality of IIL gates are arranged.
発明が解決しようとする課題 この図において、各々のIILゲート群のインジェクタ
電源端子4,8に流れ込むインジェクタ電流を11,12、さら
にGND端子に接続された抵抗10,11を、R1,R2とするとGND
側配線端子7,9の間の電位差△Ｖは次式で表わされる。
△Ｖ＝I1R1−I2R2……（１）ただし、配線抵抗R12は無
視できるものとする。また、GND側配線抵抗7,9と全IIL
ゲート共通のGND端子13との各々を電位差をV1,V2とし
て、さらに抵抗12をR3とすると、V1,V2は次式で表わさ
れる。In this figure, let us assume that injector currents flowing into injector power supply terminals 4 and 8 of each IIL gate group are 11 and 12, and resistors 10 and 11 connected to GND terminals are R1 and R2. GND
The potential difference ΔV between the side wiring terminals 7 and 9 is expressed by the following equation.
ΔV = I 1 R 1 −I 2 R 2 (1) However, it is assumed that the wiring resistance R12 can be ignored. In addition, GND side wiring resistance 7, 9 and all IIL
Assuming that the potential difference between each of the GND terminal 13 and the common gate is V 1 and V 2 and the resistance 12 is R 3 , V 1 and V 2 are represented by the following equations.
V1＝I1R1＋（I1＋I2）R3 ……（２） V2＝I2R2＋（I1＋I2）R3 ……（３） そこで、２個のIIL群のIILゲートの飽和電圧を考察す
ると、飽和電圧の差△VCE（SAT）は次式で表わすことが
できる。V 1 = I 1 R 1 + (I 1 + I 2 ) R 3 ... (2) V 2 = I 2 R 2 + (I 1 + I 2 ) R 3 ... (3) Considering the saturation voltage of the IIL gate, the saturation voltage difference ΔV CE (SAT) can be expressed by the following equation.
△VCE（SAT）＝〔VCE1（SAT）＋V1〕 −〔VCE2（SAT）＋V2〕 ＝VCE1（SAT）−VCE2（SAT）＋△Ｖ ……（４） ここでVCE1（SAT）,VCE2（SAT）は各々２つの群に属
するIILゲートの飽和電圧である。個々のIILゲートのイ
ンジェクタ電流は等しくなるように設定するのは一般的
であり、VCE1（SAT）〜VCE2（SAT）とすると、△VCE（S
AT）〜△Ｖとなる。この△Ｖの絶対値を小さくするため
に、通常はアルミニウム配線幅を太くして抵抗の絶対値
を小さくするが、チップ面積が増大したり、配置設計の
自由度が少なくなり、さらに△Ｖが無視できる程度に小
さくできるならばIILゲートの遅延時間のばらつきを生
じる。ΔV CE (SAT) = [V CE1 (SAT) + V 1 ] − [V CE2 (SAT) + V 2 ] = V CE1 (SAT) −V CE2 (SAT) + ΔV (4) where V CE1 (SAT) and V CE2 (SAT) are the saturation voltages of the IIL gates belonging to two groups. In general, the injector current of each IIL gate is set to be equal. If V CE1 (SAT) to V CE2 (SAT), △ V CE (S
AT) to ΔV. In order to reduce the absolute value of ΔV, the width of the aluminum wiring is generally widened to reduce the absolute value of the resistance. However, the chip area increases, the degree of freedom in layout design decreases, and ΔV further decreases. If it can be made negligible, the delay time of the IIL gate will vary.
したがって、本発明は上述の欠点を解決したIILゲー
トのGND配線の構造を提供することを目的とする。Therefore, an object of the present invention is to provide a structure of a GND wiring of an IIL gate which has solved the above-mentioned disadvantages.
課題を解決するための手段 本発明は、複数個のIILゲートからなる単位のIILゲー
ト群を複数に有し、前記単位IILゲート群の各接地側配
線から引き出された各金属薄膜配線抵抗の平面的な形状
を前記各ゲート群の接地側配線に流れる電流に応じて変
えて成るIIL素子である。Means for Solving the Problems The present invention has a plurality of IIL gate groups of a unit composed of a plurality of IIL gates, and the plane of each metal thin film wiring resistance drawn from each ground side wiring of the unit IIL gate group. This is an IIL element in which the basic shape is changed according to the current flowing through the ground side wiring of each gate group.
作用 本発明によると、金属配線の形状を変えてIILゲート
群の配置設計に自由度をもたせることにより、配置設計
の時間短縮やチップサイズの小型化を実現し、チップ上
の各IIL素子の飽和電圧の均一化ならびにゲート遅延時
間の均一化を実現することができる。According to the present invention, by changing the shape of the metal wiring to allow the degree of freedom in the layout design of the IIL gate group, it is possible to shorten the layout design time and reduce the chip size, and to saturate each IIL element on the chip. It is possible to make the voltage uniform and the gate delay time uniform.
実施例 つぎに、本発明を第１図〜第３図の各実施例回路図、
特性図に照して、実施例によって詳しく説明する。Embodiments Next, the present invention will be described with reference to the circuit diagrams of FIGS.
An example will be described in detail with reference to a characteristic diagram.
第１図において、GND端子7,9とGND端子13間の電位差V
1,V2を下げる。すなわち、アルミニウム配線抵抗を小さ
くするために、配線長を短くしたり、配線幅を広げたり
するが本発明に従うと第１図において、R1I1＝R2I2にに
なるように配線抵抗を選定する。すなわち、GNDの共通
抵抗R12もしくは共通のGND端子と、複数個のIILゲート
からなる複数のIILゲート群のGND側配線端子間に接続さ
れるアルミニウム配線抵抗を各々の群インジェクタ電流
に反比例されるように選定することにより、アルミニウ
ム配線の形状を変えてIILゲート群の配置設計に自由度
をもたせたり、IILゲートの遅延時間のばらつきをおさ
えることができる。第２図は本発明の実施例のICの平面
図を示す。IILゲート５を用いたIC,LSIチップ14におい
て、IILゲート群１のゲート数がIILゲート群２のゲート
数より多い場合、GND側配線端子7,9に接続するアルミニ
ウム配線抵抗値をゲート数に反比例するように、またII
Lゲート群１のゲート数がIILゲート群２のゲート数より
少ない場合にはゲート数に比例するように、各金属薄膜
配線の相対比を維持しながら、配置設計の手段としてこ
れら金属配線抵抗の長さと幅を調整し、GND側配線端子
7,9の電位を等しくしたものである。In FIG. 1, the potential difference V between GND terminals 7, 9 and GND terminal 13 is shown.
1, lowering the V 2. That is, in order to reduce the aluminum wiring resistance, the wiring length is shortened or the wiring width is increased. However, according to the present invention, the wiring resistance is set so that R 1 I 1 = R 2 I 2 in FIG. Is selected. That is, the aluminum wiring resistance connected between the GND common resistor R12 or the common GND terminal and the GND-side wiring terminals of a plurality of IIL gate groups including a plurality of IIL gates is inversely proportional to each group injector current. By changing the shape of the aluminum wiring, the degree of freedom in the layout design of the IIL gate group can be increased, and variations in the delay time of the IIL gate can be suppressed. FIG. 2 is a plan view of an IC according to an embodiment of the present invention. When the number of gates of the IIL gate group 1 is larger than the number of gates of the IIL gate group 2 in the IC or LSI chip 14 using the IIL gate 5, the resistance value of the aluminum wiring connected to the GND side wiring terminals 7, 9 is converted to the number of gates. Inversely proportional, and II
When the number of gates in the L gate group 1 is smaller than the number of gates in the IIL gate group 2, while maintaining the relative ratio of each metal thin film wiring so as to be proportional to the number of gates, as a means of layout design, these metal wiring resistances are reduced. Adjust the length and width, and connect the GND side wiring terminal
The potentials of 7, 9 are equalized.
第３図は各ゲートの電位をチップ上の位置との関係で
図示したものである。GND電位ｂとｂ′の左端3,3′での
電位が等しくなる場合を示している。FIG. 3 shows the potential of each gate in relation to the position on the chip. This shows a case where the potentials at the left ends 3, 3 'of the GND potentials b and b' are equal.
発明の効果 本発明によりIIL素子を用いたIC,LSIにおいて配置設
計に自由度をもたせたりチップ面積の小型化をはかった
り、また飽和電圧の均一化を達成することができる。前
記のように金属配線の形状を変えてIILゲート群の配置
設計に自由度をもたせることにより配置設計の時間短縮
やチップサイズの小型化の実現だけでなく、遅延時間の
ばらつきに起因する理論上の誤動作を防止しゲート遅延
時間の均一化を実現することができる。Effects of the Invention According to the present invention, in an IC or LSI using an IIL element, it is possible to provide a degree of freedom in layout design, to reduce a chip area, and to achieve a uniform saturation voltage. By changing the shape of the metal wiring as described above and giving the degree of freedom to the layout design of the IIL gate group, not only shortening of the layout design and miniaturization of the chip size, but also theoretically due to the variation of the delay time Can be prevented, and the gate delay time can be made uniform.
第１図は本発明実施例を模型的に表わした等価回路図、
第２図は本発明実施例の平面図、第３図は同実施例の配
線上の電位分布特性図、第４図は従来例装置を模型的に
表わした平面図、第５図は第４図示装置の要部電位分布
特性図である。 １……複数個IILゲート、２……他の複数個IILゲート、
３……インジェクタ電流供給用金属配線、4,8……イン
ジェクタ端子、５……IILゲート、６……GND側金属配
線、7,9……各IILゲート群のGND側配線端子、10,11……
金属配線抵抗、12……GND端子13側の金属配線抵抗、14
……半導体チップ。FIG. 1 is an equivalent circuit diagram schematically showing an embodiment of the present invention,
FIG. 2 is a plan view of an embodiment of the present invention, FIG. 3 is a potential distribution characteristic diagram on wiring of the embodiment, FIG. 4 is a plan view schematically showing a conventional example device, and FIG. It is a principal part electric potential distribution characteristic figure of the illustration apparatus. 1 ... multiple IIL gates, 2 ... other multiple IIL gates,
3 ... metal wiring for injector current supply, 4,8 ... injector terminal, 5 ... IIL gate, 6 ... metal wiring on the GND side, 7, 9 ... wiring terminal on the GND side of each IIL gate group, 10, 11 ......
Metal wiring resistance, 12: Metal wiring resistance on GND terminal 13 side, 14
... Semiconductor chips.
Claims (1)
ト群を複数に有し、前記単位IILゲート群の各接地側配
線から引き出された各金属薄膜の配線抵抗の他端を共通
の接地端子とし、前記各ゲート群の接地側配線に流れる
電流に応じて当該金属配線抵抗の平面的な形状を変えて
成るIIL素子。A plurality of IIL gate groups each comprising a plurality of IIL gates, and the other end of the wiring resistance of each metal thin film drawn from each ground side wiring of the unit IIL gate group is connected to a common ground. An IIL element comprising a terminal, and changing a planar shape of the metal wiring resistance according to a current flowing through a ground-side wiring of each of the gate groups.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63016083A JP2624280B2 (en) | 1988-01-27 | 1988-01-27 | IIL element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63016083A JP2624280B2 (en) | 1988-01-27 | 1988-01-27 | IIL element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01191467A JPH01191467A (en) | 1989-08-01 |
| JP2624280B2 true JP2624280B2 (en) | 1997-06-25 |
Family
ID=11906652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63016083A Expired - Lifetime JP2624280B2 (en) | 1988-01-27 | 1988-01-27 | IIL element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2624280B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55107256A (en) * | 1979-02-08 | 1980-08-16 | Mitsubishi Electric Corp | Iil integrated circuit device |
| JPS61214558A (en) * | 1985-03-20 | 1986-09-24 | Hitachi Ltd | Semiconductor device |
-
1988
- 1988-01-27 JP JP63016083A patent/JP2624280B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01191467A (en) | 1989-08-01 |
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