JP2546845B2 - Master-slice type semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a master slice semiconductor integrated circuit having a power supply pad in the peripheral portion of a chip and having a plurality of logic circuit cells arranged in an array therein. Regarding the circuit.

[Conventional technology]

Conventionally, a chip structure of this type of master slice type semiconductor integrated circuit has, as shown in an example in FIG. 3, a plurality of logic circuit cells (hereinafter referred to as cells) in two directions orthogonal to each other over the entire chip 101. They are arranged in an array and each form a plurality of rows and columns. Chip 101
The power supply pads 102 are arranged along the four sides of the above, and a required wiring is installed between the respective logic circuit cells as an inter-cell wiring region 105 in the middle of each logic circuit cell row 104. FIG. 4 (a),
(B) of the cells housed in the chip 101 of the conventional example, a cell 103 installed near the power pad 102 and a cell installed far from the power pad 102 at the center of the chip 101. The structure of the ECL circuit accommodated in 106 is shown, and both have the same structure and function except the applied voltage difference due to the wiring distance difference from the power supply pad 102. Therefore, the resistors 7 ₁ , 7 ₂ , 108, and 109 in the figure respectively
Both cells 103 and 106 have the same resistance value.

In this ECL circuit, two transistors 2 and 3 are connected in parallel to one side of a differential amplifier section to form an input side of an OR gate, and a signal A and a signal B are input from the outside to respective bases. The reference voltage V _REF is applied to the base of the other pair of transistors 4, and when the input voltage of either the signal A or the signal B is lower than the reference voltage V _REF , the transistor 4 is turned on and the transistors 2 and 3 are turned on. Is turned off, the base current is not supplied to the output transistor 6, the output transistor 6 is turned off, and the output A + B becomes "L" level. Next, the input voltage of either signal A or B is the reference voltage.
When it is higher than V _REF , the transistor 2 or 3 is turned on, the transistor 4 is turned off, and the output transistor 6 is turned on contrary to the previous state, and the output A + B becomes “H” level. The transistor 5 has a constant base voltage V _CS
It is turned on by this to make the differential amplifier circuit a constant current.

[Problems to be solved by the invention]

The chip structure of the conventional master slice type semiconductor integrated circuit described above has a difference in the power supply voltage supplied to each cell depending on the position where it is arranged due to the power supply potential drop with respect to each cell that occurs in the actual use state. If cells having the same element and the same circuit constant are arranged, a difference occurs in the circuit current due to the difference in the power supply voltage, and as a result, the characteristics vary.

In FIG. 4, the actual ground potential V _gnd and power supply potential V _ee supplied to each cell 103, 106 are the power supply from the ground potential V _GND and power supply potential V _EE at the power supply pad 102 to the power supply terminal of the cell. The potential drop ΔV _gnd and the potential rise ΔV _ee due to the wiring are expressed by the following equations.

V _gnd = V _GND −ΔV _gnd , V _ee = V _EE + ΔV _ee Therefore, for each of the cells 103 and 106, the resistances 7 ₁ , 7 ₂ , 10
Since the resistance values of 8 and 109 are common, the currents I _CS and I _EF differ according to the magnitudes of the potential drop ΔV _gnd and the potential rise ΔV _ee as shown in the following equation. Here, for simplification, the base voltage V _CS , the reference voltage V _REF, and the base-emitter voltage V _BE of the transistor are both the cells 103 and 106.
Both are constant.

I _CS103 = [V _CS- (V _EE + ΔV _ee103 ) -V _BE ] / R _E I _CS106 = [V _CS − (V _EE + ΔV _ee106 ) -V _BE ] / R _E I _EF103 = [(V _GND − ΔV _gnd103 ) −V _BE −V _EE ] / R _EF I _EF106 = [(V _GND −ΔV _gnd106 ) −V _BE −V _EE ] / R _EF However, subscripts 103 and 106 refer to cells 103 and 106, respectively. , R _E and R _EF are the emitter resistance 108
And 109 resistance.

_Regarding the magnitudes of the potential drop ΔV _gnd and the potential rise ΔV _ee , there is a large difference between the cell 103 arranged in the peripheral part of the chip 101 and the cell 106 arranged in the central part of the chip 101, and the cell size is further reduced. Since the wiring pattern for power supply is reduced as much as possible, the difference becomes larger and larger, so that the electrical characteristics, especially the gate delay vary depending on the cell position.

By the way, as the integrated circuit becomes ultra-miniaturized and highly densified, the cell size is being reduced. Therefore, it is desirable to reduce the wiring pattern used for voltage application as much as possible.

An object of the present invention is to eliminate the above-mentioned drawbacks and provide a master slice type semiconductor integrated circuit having a cell structure having stable electric characteristics even if a power supply wiring pattern is reduced to some extent and a potential drop or a potential rise is increased. That is.

[Means for solving problems]

The master slice type semiconductor integrated circuit of the present invention has a resistance value for compensating the influence of the applied voltage difference for each cell, corresponding to the applied voltage difference to each cell due to the wiring distance difference from the power supply pad to each cell. Has a set resistance.

[Action]

Thus, even if the wiring distance from the power supply pad varies depending on the position where each cell in the chip is arranged, the resistance value of the resistance element in the cell is adjusted in advance in response to this. As a result, the difference in the applied voltage based on the difference in the wiring distance can be compensated, and all the cells can have the same electric characteristics.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) and 1 (b) are cells 1 used in one embodiment of the master slice type semiconductor integrated circuit of the present invention, each of which is placed near a power supply pad.
And a circuit diagram showing the internal element structure of a cell 10 arranged at a substantially central portion of the chip, that is, at a position distant from the power supply pad. FIG. 2 (a) shows the emitter resistors 8 and 9 of FIG. 1 (a). 2 (b) is an external view of the emitter resistors 11 and 12 of FIG. 1 (b).

In this embodiment, all the cells 103, 106, etc. in the chip 101 of the conventional example of the master slice type semiconductor integrated circuit of FIG. 3 described above are the cells illustrated in FIG. 1 (a), (b). It is replaced with 1, 10, etc., and other configurations are the same.

Now, the cell 1 near the power supply pad 102 is the cell 103 of the conventional example.
The cell 10 at the center corresponds to the cell 106 of the conventional example, and the cells 1 and 10 have the same EL as the cells 103 and 106, respectively.
Although it has a C circuit configuration and therefore has a similar circuit configuration, the distribution of the respective resistance values of the emitter resistors 8, 9 and 11, 12 is similar to that of the conventional emitter resistors 108, 109 and 111, 112.
The distribution of each resistance value is different.

Similar to the conventional example, the output currents flowing through the differential amplifiers and the output of cells 1 and 10 are I _CS1 , I _CS10 and I _EF1 , I _{EF10, respectively.}
And the resistance values of the emitter resistors 8, 9, 11, and 12 are R _E1 , R _E10 , and R _EF10 , respectively, I _CS1 = [V _CS − (V _EE −ΔV _ee1 ) −V _BE ] / R _E1 I _{CS10 = [V CS - (V} EE -ΔV ee10) -V bE] / R E10 where the following equation only to be fully in order to I _CS1 = I _CS10 is established.

On the other hand, I _EF1 = [(V _GND −ΔV _gnd1 ) −V _BE −V _EE ] / R _EF1 I _EF10 = [(V _GND −ΔV _gnd10 ) −V _BE −V _EE ] / R _EF10 where I _EF1 = I _In order for _{EF10 to} be established, the following formula should be satisfied.

[Delta] V _GND1 in the above formula, [Delta] V _{the GND 10} and [Delta] V _ee1, [Delta] V
_ee10 indicates the voltage drop and the voltage rise to the cells 1 and 10, respectively, and V _GND and V _EE are the ground potential and the power supply potential to the power supply pad 102, respectively.

Accordingly, in this embodiment, in order to I _CS1 = I _CS10, from equation (1) because it is _ΔV ee10> ΔV _ee1, R
_It is necessary to _{satisfy E1} > R _E10 , and in order to _satisfy I _EF1 = I _EF10 , ΔV _gnd10 > ΔV _{gnd1. Therefore} , from the formula (2), it is necessary to _satisfy R _EF1 > R _EF10 . Here, as shown in FIGS. 2A and 2B, the contact portions 17, 22 of the resistance layers 15, 20 are connected to the emitter resistors 8, 9 of the cell 1 and the emitter resistors 11, 12 of the cell 10. By adjusting the position of, the predetermined resistance values R _E1 , R that satisfy the relations of equations (1) and (2)
Got _EF1 , R _E10 , R _EF10 . At that time, contact part 1
Even if the positions of 7 and 22 are different, aluminum terminal parts 14 and 1 that cover it
Notice that the nines are equal in size. By doing so, the wiring patterns drawn from the cells 1 and 10 can be the same regardless of the resistance values of the cells 1 and 10, and from the viewpoint of the wiring process, the power supply pad 10 can be used.
Cell 1 located far from 2 also has power pad 1
The cell 10 arranged at a position far from 02 can be treated as the same cell.

In the above description, the cell 1 and the cell 10 are taken as an example to describe the configuration and operation, but the same applies to each of the other cells.

〔The invention's effect〕

As described above, according to the present invention, the resistance value in each cell is corrected in advance in the diffusion process in accordance with the potential drop of the power supply supplied to each cell, which is expected in actual use. Since the circuit current flowing through the cells can be made substantially uniform, there is an effect that the electrical characteristics of all cells can be made uniform in the chip.

[Brief description of drawings]

1A and 1B show, among cells used in one embodiment of the master slice type semiconductor integrated circuit of the present invention, a cell 1 arranged near the power supply pad 102 and a position separated from the power supply. 2 is a circuit diagram showing the internal element configuration of the cell 10 arranged in FIG. 2, FIG. 2 (a) is an external view of the emitter resistors 8 and 9 in FIG. 1 (a), and FIG. 2 (b) is FIG. (B)
3 is an external view of the emitter resistors 11 and 12 in FIG. 3, FIG. 3 is a view showing a chip structure of a conventional example of a master slice type semiconductor integrated circuit, and FIGS. 4 (a) and 4 (b) are power supplies in FIG. 3, respectively. 6 is a circuit diagram showing an internal element configuration of a cell 103 arranged at a position close to a pad 102 and a cell 106 arranged at a position distant from a power supply. FIG. 1, 10 ... Cell, 2, 3, 4, 5, 6 ... Transistor, 7 ₁ , 7 ₂ ... Collector resistance, 8, 9, 11, 12 ... Emitter resistance, 13, 14, 18, 19 ... … Aluminum terminal part, 15, 20 …… Resistance layer, 16,17,21,22 …… Contact part, 101 …… Chip, 102 …… Power supply pad, A, B …… Input, V _EE …… Power supply potential, V _GND ...... ground _potential, ΔV _ee1, ΔV ee10 ...... potential _rise, ΔV gnd1, ΔV gnd10 ...... potential drop, V _REF ...... reference voltage, V _CS ...... base voltage, I _CS1, I _CS10 ...... differential Amplifier circuit current, I _EF1 , I _EF10 …… Output circuit current.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 19/177

Claims (1)

(57) [Claims] 1. A master slice type semiconductor integrated circuit having a power supply pad in the peripheral portion of a chip and having a plurality of logic circuit cells arranged in an array therein, wherein a wiring distance difference from the power supply pad to each cell is different. Irrespective of the difference in the voltage applied to each cell due to the difference in the wiring distance from the power supply pad to each cell, the resistance value of the internal resistance of each cell is substantially Is set, the internal resistance of each cell has a resistance layer, an electrode terminal portion and a contact portion that connects a part of the resistance layer to the electrode terminal portion, and the resistance layer and the electrode terminal portion are A master slice characterized in that the position of the contact portion is changed while being the same between cells, and the resistance value of the internal resistance required for each cell is set by this. Formula semiconductor integrated circuit.