JPS6256666B2 - - Google Patents

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Publication number
JPS6256666B2
JPS6256666B2 JP8040881A JP8040881A JPS6256666B2 JP S6256666 B2 JPS6256666 B2 JP S6256666B2 JP 8040881 A JP8040881 A JP 8040881A JP 8040881 A JP8040881 A JP 8040881A JP S6256666 B2 JPS6256666 B2 JP S6256666B2
Authority
JP
Japan
Prior art keywords
resistance
diffusion layer
pinch
region
type diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8040881A
Other languages
Japanese (ja)
Other versions
JPS57196558A (en
Inventor
Atsushi Kishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP8040881A priority Critical patent/JPS57196558A/en
Priority to DE8282104644T priority patent/DE3273527D1/en
Priority to EP82104644A priority patent/EP0066263B2/en
Publication of JPS57196558A publication Critical patent/JPS57196558A/en
Priority to US06/867,422 priority patent/US4725876A/en
Publication of JPS6256666B2 publication Critical patent/JPS6256666B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802Resistors only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/8605Resistors with PN junctions

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は半導体集積回路のピンチ抵抗に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pinch resistor for a semiconductor integrated circuit.

近来世界的エネルギー危機から省エネルギー化
が提唱されている。この大きな課題のにない手と
なつているのが半導体集積回路の導入である。
Energy saving has been advocated due to the recent global energy crisis. The introduction of semiconductor integrated circuits is a promising solution to this major problem.

半導体集積回路も同理由より年々回路電流の減
少化が進んでいる。これには最近の高集積化に伴
なうパツケージ熱抵抗などの問題も含まれている
が、高抵抗の素子を用いた動作電流の減少が重要
な課題となつている。このため、今後、半導体集
積回路、特にリニア集積回路の分野ではI2Lの積
極的導入など能動素子の面での小電流化と受動素
子である抵抗の高抵抗化による小電流化の傾向に
ある事はいうまでもない。
For the same reason, the circuit current of semiconductor integrated circuits is decreasing year by year. This includes problems such as package thermal resistance due to the recent trend toward higher integration, but the reduction of operating current using high-resistance elements has become an important issue. Therefore, in the future, in the field of semiconductor integrated circuits, especially linear integrated circuits, there will be a trend toward smaller currents in terms of active elements, such as the active introduction of I 2 L, and lower currents by increasing the resistance of resistors, which are passive elements. It goes without saying that there is one thing.

ここで問題になるのが絶対精度より相対精度を
要する高抵抗である。本発明は半導体集積回路の
中で高抵抗として最も用いられているピンチ抵抗
の相対比の改善に関するものである。なお、以下
に、抵抗の比精度のことを相対比と呼ぶ。
The problem here is high resistance, which requires relative accuracy rather than absolute accuracy. The present invention relates to improving the relative ratio of pinch resistance, which is most used as a high resistance in semiconductor integrated circuits. Note that, hereinafter, the relative accuracy of the resistance will be referred to as a relative ratio.

本願の説明に入る前に参考の為、一般的なピン
チ抵抗について簡単に第1図、第2図をもつて説
明する。ピンチ抵抗はトランジスタのエミツタ2
直下のベース領域1の高抵抗を利用するもので、
P型基板6上のN型エピタキシヤル層にP型ベー
ス領域の拡散と同時に形成される拡散層1を設
け、この中にN+エミツタ領域の拡散と同時に形
成される拡散層2をつくつてP型拡散層1の厚さ
を減少させると同時にP型拡散層1の表面の高濃
度部分にN+型拡散層2を重畳してこの高濃度部
分が抵抗値に寄与しない形となつている。電極3
は表面酸化膜4の開孔を通してP型拡散層1の両
端から導出される。尚1′,2′は各拡散層1,2
の横方向拡がり分を示したものである。
Before entering into the description of the present application, a general pinch resistor will be briefly explained with reference to FIGS. 1 and 2 for reference. The pinch resistor is the emitter 2 of the transistor.
This utilizes the high resistance of the base area 1 directly below.
A diffusion layer 1 formed at the same time as the diffusion of the P type base region is provided in the N type epitaxial layer on the P type substrate 6, and a diffusion layer 2 formed at the same time as the diffusion of the N + emitter region is formed in this layer. At the same time, the thickness of the type diffusion layer 1 is reduced, and the N + type diffusion layer 2 is superimposed on the high concentration portion of the surface of the P type diffusion layer 1, so that this high concentration portion does not contribute to the resistance value. Electrode 3
are led out from both ends of the P-type diffusion layer 1 through the openings in the surface oxide film 4. Note that 1' and 2' are the respective diffusion layers 1 and 2.
This shows the lateral spread of .

この為、N+拡散層2の直下の層抵抗がN+拡散
層2の形成前のP型拡散層1の層抵抗より1ケタ
程度大きく層抵抗ρS=1kΩ/□〜10kΩ/□と
なる。又ピンチ抵抗の精度は同時に形成するnPn
トランジスタのベース幅に等しく、nPnトランジ
スタのhFEに依存するため大きくバラツいてしま
う。このバラツキ幅は通常のnPnトランジスタの
ベース拡散抵抗より大きいものである。
Therefore, the layer resistance directly under the N + diffusion layer 2 is about one order of magnitude larger than the layer resistance of the P type diffusion layer 1 before the formation of the N + diffusion layer 2, and the layer resistance ρ S = 1 kΩ/□ ~ 10 kΩ/□. . In addition, the accuracy of the pinch resistance is determined by the nPn formed at the same time.
It is equal to the base width of the transistor, and varies widely because it depends on the hFE of the nPn transistor. This variation width is larger than the base diffusion resistance of a normal nPn transistor.

しかしながら差動増幅器の負荷用又はブリーダ
ー抵抗として通常のベース拡散抵抗と同様抵抗比
で決まる回路構成とすれば抵抗のバラツキによる
特性変動は実用範囲内に納まる。
However, if the load or bleeder resistor of a differential amplifier is configured in a circuit that is determined by the resistance ratio like a normal base diffused resistor, the characteristic fluctuations due to resistance variations will be within the practical range.

次に上記のごとく高抵抗で抵抗比をとる場合を
ピンチ抵抗とベース拡散抵抗について述べる。
Next, we will discuss pinch resistance and base diffused resistance when taking a resistance ratio with high resistance as described above.

高抵抗設計においてベース拡散抵抗は抵抗の層
抵抗ρSが低い(ρS=100Ω/□〜300Ω/□)為
抵抗長が非常に長くなり抵抗幅、コーナー数をそ
ろえれば拡散横広がり、コンタクト抵抗などのバ
ラツキ、ズレによる抵抗値に対する影響がほぼ無
視でき相対比をとる上で利点となつている。反面
抵抗長が長い為ペレツト上での占有面積が大き
く、ペレツト縮少化の面から無視できない。
In high-resistance design, the base diffused resistor has a low resistance layer resistance ρ SS = 100 Ω/□ ~ 300 Ω/□), so the resistance length becomes very long, and if the resistance width and number of corners are made the same, the diffusion spreads laterally and the contact The influence on the resistance value due to variations and deviations in resistance etc. can be almost ignored, which is an advantage in calculating relative ratios. On the other hand, since the resistance length is long, it occupies a large area on the pellet, which cannot be ignored from the viewpoint of reducing pellet size.

これに対して、ピンチ抵抗を用いると前記理由
により抵抗の層抵抗ρSが高く(ρPINCH=1k
Ω/□〜10kΩ/□)、抵抗長が短くなり、ペレ
ツト上での占有面積を小さくできるが、抵抗長が
短い分前述した拡散横広がりが抵抗値に影響し、
ピンチ抵抗の相対比をとる事が困難だつた。
On the other hand, when a pinch resistor is used, the layer resistance ρ S of the resistor is high (ρ PINCH = 1k
Ω/□~10kΩ/□), the resistance length becomes shorter and the area occupied on the pellet can be reduced, but because the resistance length is short, the above-mentioned lateral spread of diffusion affects the resistance value.
It was difficult to determine the relative ratio of pinch resistance.

次に2つのピンチ抵抗の抵抗比精度を上げる従
来技術について述べる。
Next, a conventional technique for increasing the resistance ratio accuracy of two pinch resistors will be described.

第3図は1つの半導体基体上に同一拡散工程で
2つのピンチ抵抗R1,R2を形成したもので、
P型拡散層12,17は抵抗R1では3回、抵抗
R2では4回折れ曲つて形成されている。N+
散層14,19はそれぞれP型拡散層12とは3
回、P型拡散層17とは4回重複するように形成
されている。12′,17′,14′,19′はそれ
ぞれ拡散層12,17,14,19の横拡がりに
よる誤差を示したものである。電極16,21は
それぞれP型拡散層12,17の両端から取り出
されている。
Figure 3 shows two pinch resistors R1 and R2 formed on one semiconductor substrate in the same diffusion process.
The P-type diffusion layers 12 and 17 are bent three times for the resistor R1 and four times for the resistor R2. The N + diffusion layers 14 and 19 are different from the P type diffusion layer 12, respectively.
It is formed so as to overlap with the P-type diffusion layer 17 four times. 12', 17', 14', and 19' indicate errors due to lateral expansion of the diffusion layers 12, 17, 14, and 19, respectively. Electrodes 16 and 21 are taken out from both ends of P-type diffusion layers 12 and 17, respectively.

このようなピンチ抵抗R1,R2の抵抗比を次
に検討するピンチ抵抗R1の抵抗値の簡略式を(1)
式に示す。ここでP型拡散層12の層抵抗ρS
前述のごとく約100%〜−50%でバラツくが同一
ウエハー上ではほぼ一定である。また、同様に目
ずれ、オーバーエツチングについても同一ウエハ
ー上では一定と考えることができる。
The resistance ratio of the pinch resistors R1 and R2 will be considered next.The simplified formula for the resistance value of the pinch resistor R1 is given by (1)
As shown in Eq. Here, the layer resistance ρ S of the P-type diffusion layer 12 varies from about 100% to -50% as described above, but is almost constant on the same wafer. Similarly, misalignment and overetching can be considered to be constant on the same wafer.

ρPINCH:P型拡散層の層抵抗ρS LL1L2L3:マスク上のN+拡散層の長さ ΔLΔL1ΔL2ΔL3:拡散後のN+拡散層の横広が
り分 W:マスク上のP型拡散層の幅 ΔW:拡散後のP型拡散層の横広がり分 α:コンタクト部の接触抵抗とN+型拡散層と
重複していないP型拡散層の抵抗 (1)式で2項は1項に比べ一般に無視できるので
(1)式は(1)′式となる。
ρ PINCH : Layer resistance of P-type diffusion layer ρ S LL 1 L 2 L 3 : Length of N + diffusion layer on mask ΔLΔL 1 ΔL 2 ΔL 3 : Lateral spread of N + diffusion layer after diffusion W: Mask Width of the upper P-type diffusion layer ΔW: Lateral spread of the P-type diffusion layer after diffusion α: Contact resistance of the contact portion and resistance of the P-type diffusion layer that does not overlap with the N + type diffusion layer (1) Since the second term can generally be ignored compared to the first term,
Equation (1) becomes equation (1)'.

同様にピンチ抵抗R2については(2)式が成り立
ここで説明を簡単にする為抵抗幅W=W′、抵
抗長L1+L2+L3=L4+L5+L6+L7=Lとすると
抵抗の相対比R2/R1は(3)式となる。
Similarly, equation (2) holds true for pinch resistance R2. To simplify the explanation here, assuming that the resistance width W = W' and the resistance length L 1 +L 2 +L 3 =L 4 +L 5 +L 6 +L 7 =L, the relative ratio of resistance R 2 /R 1 is calculated by formula (3). becomes.

N+拡散層の拡散後の横広がりは同一ウエハー
上では同じであるから、ΔL=ΔL1=ΔL2=Δ
L3=ΔL4=ΔL5=ΔL6=ΔL7となり、(3)式は(4)
式となる。
Since the lateral spread of the N + diffusion layer after diffusion is the same on the same wafer, ΔL = ΔL 1 = ΔL 2 = Δ
L 3 = ΔL 4 = ΔL 5 = ΔL 6 = ΔL 7 , and equation (3) becomes (4)
The formula becomes

/R=4ΔL+L/3ΔL+L …(4) (4)式で4ΔLと3・ΔLが相対比の誤差の要因
となつている。すなわちピンチ抵抗R2,R1のマ
スク上での抵抗長Lをそろえても(4)式の誤差を生
じる。
R 2 /R 1 =4ΔL+L/3ΔL+L (4) In equation (4), 4ΔL and 3·ΔL are the causes of the error in the relative ratio. That is, even if the resistance lengths L of the pinch resistors R 2 and R 1 on the mask are made the same, an error as shown in equation (4) occurs.

(4)式を一般式にあてはめると(5)式となる。この
とき抵抗幅は等しいとする。
Applying equation (4) to the general equation yields equation (5). At this time, the resistance widths are assumed to be equal.

ここで、 n:抵抗R1のN+拡散層とP型拡散層との重
複部分の数 n′:抵抗R2のN+拡散層とP型拡散層との重
複部分の数 β:抵抗R1のP型拡散層の長さと抵抗R2の
P型拡散層の長さの比例定数 (5)式は相対比をとる抵抗のN+拡散層とP型拡
散層との重複する部分の数が異なるほど相対比が
ずれることを表わしている。
Here, n: Number of overlapping parts between the N + diffusion layer of resistor R1 and the P-type diffusion layer n': Number of overlapping parts between the N + diffusion layer and P-type diffusion layer of resistor R2 β: P of resistor R1 The proportionality constant of the length of the type diffusion layer and the length of the P type diffusion layer of the resistance R2 , Equation (5), takes a relative ratio. This indicates that the ratio is off.

このような抵抗R1,R2の抵抗値の相対比の
ズレをなくすには、(5)式のnとn′の数を等しくす
れば良く、第3図の例ではP型拡散層12と17
の折れ曲がる回数を等しくすれば良いことにな
る。しかしながら、nとn′の数を等しくすれば、
抵抗R1と抵抗R2との抵抗値が等しい時のみ抵
抗値の相対比のズレがなくなることとなり、任意
の抵抗比のズレをなくすことはできない。
In order to eliminate such a difference in the relative ratio of the resistance values of the resistors R1 and R2, it is sufficient to make the numbers n and n' in equation (5) equal, and in the example of FIG.
It is sufficient to make the number of bends of the two parts equal. However, if we make the numbers n and n′ equal, then
Only when the resistance values of the resistors R1 and R2 are equal, there is no difference in the relative ratio of resistance values, and it is not possible to eliminate any difference in the resistance ratio.

本発明はこの様な欠点をのぞくものでマスクレ
イアウト上で相対比をとるピンチ抵抗のベース形
状を自由に設定でき、精度良く抵抗の相対比がと
れる事を目的としたものである。
The present invention eliminates these drawbacks, and aims to allow the base shape of the pinch resistor for which the relative ratio is to be determined on the mask layout to be freely set, and to enable the relative ratio of the resistors to be determined with high accuracy.

すなわち、本発明によれば、一導電型領域に重
畳する他の導電型領域を有するピンチ抵抗を複数
個有し、該複数個のピンチ抵抗の抵抗比とそれぞ
れのピンチ抵抗で一導電型領域に他の導電型領域
が重畳する数の比がほぼ等しい半導体集積回路装
置を得る。
That is, according to the present invention, there is provided a plurality of pinch resistors each having a region of another conductivity type superimposed on a region of one conductivity type, and the resistance ratio of the plurality of pinch resistors and the respective pinch resistors are used to form a region of one conductivity type. A semiconductor integrated circuit device is obtained in which the ratio of the number of overlapping regions of other conductivity types is approximately equal.

次に、図面を参照して本発明をより詳細に説明
する。
Next, the present invention will be explained in more detail with reference to the drawings.

第4図は本発明の一実施例を示す平面図で、例
えばN型エピタキシヤル層に2つのピンチ抵抗R
3とR4とが形成されている。ピンチ抵抗R3は
P型ベース領域と同一拡散工程で形成されるP型
拡散層50と、これと表面部分で重複するN+
散層51とを有している。P型拡散層50はU字
状に折れ曲がり、両端に電極取出部52を備えて
いる。N+拡散層51はN+型エミツタ領域と同一
拡散工程で形成され、P型拡散層50と3回重複
するようにU字状に形成されている。ピンチ抵抗
R4はやはりP型ベース領域と同一拡散工程で形
成されるP型拡散層53と、N+型エミツタ領域
と同一拡散工程で形成されるN+拡散層54とを
有し、N+拡散層54はP型拡散層53の表面部
分と重複するようになされている。P型拡散層5
3は2回折れ曲つており、結局N+拡散層54と
は3回重複している。P型拡散層53の両端には
電極取出し部55を有している。
FIG. 4 is a plan view showing an embodiment of the present invention, for example, two pinch resistors R are provided in an N-type epitaxial layer.
3 and R4 are formed. The pinch resistor R3 has a P-type diffusion layer 50 formed in the same diffusion process as the P-type base region, and an N + diffusion layer 51 overlapping with this in the surface portion. The P-type diffusion layer 50 is bent into a U-shape and has electrode extraction portions 52 at both ends. The N + diffusion layer 51 is formed in the same diffusion process as the N + type emitter region, and is formed in a U-shape so as to overlap the P type diffusion layer 50 three times. The pinch resistor R4 also has a P type diffusion layer 53 formed in the same diffusion process as the P type base region, and an N + diffusion layer 54 formed in the same diffusion process as the N + type emitter region . The layer 54 is arranged to overlap the surface portion of the P-type diffusion layer 53. P-type diffusion layer 5
3 is bent twice and ends up overlapping with the N + diffusion layer 54 three times. The P-type diffusion layer 53 has electrode lead-out portions 55 at both ends.

すなわち、ピンチ抵抗R3とR4との抵抗比を
“1”とした第4図の実施例では、P型拡散層5
0,53の形状にかかわらず、P型拡散層50と
N+拡散層51との重複する部分の数とP型拡散
層53とN+拡散層54との重複する部分の数が
等しくなされている。
That is, in the embodiment of FIG. 4 in which the resistance ratio of the pinch resistances R3 and R4 is "1", the P-type diffusion layer 5
Regardless of the shape of 0, 53, the P-type diffusion layer 50 and
The number of overlapping portions with the N + diffusion layer 51 and the number of overlapping portions between the P type diffusion layer 53 and the N + diffusion layer 54 are made equal.

次にこのピンチ抵抗R3とR4との抵抗比につ
いて説明する。説明を簡単にする為ピンチ抵抗を
形成するN+拡散層51,54に座標を設定し、
N+拡散層51,54直下のP型拡散層50,5
3に流れる電流の方向を「向き」、各ピンチ抵抗
のN+拡散層51,54がP型拡散層50,53
と重複している部分でのP型拡散層50,53の
電圧降下分を「大きさ」とするベクトルを想定す
る。
Next, the resistance ratio between the pinch resistors R3 and R4 will be explained. To simplify the explanation, coordinates are set for the N + diffusion layers 51 and 54 that form the pinch resistance,
P-type diffusion layers 50, 5 directly below N + diffusion layers 51, 54
3, the direction of the current flowing through the resistors is "direction", and the N + diffusion layers 51 and 54 of each pinch resistor are the P type diffusion layers 50 and 53.
Assume a vector whose "magnitude" is the voltage drop of the P-type diffusion layers 50 and 53 at the overlapped portion with .

本願では、相対比をとる抵抗R3,R4は第4
図に矢印でベクトルを示す様に、ベクトルの方向
の順序には関係なくベクトルの本数を相対比をと
る抵抗のP型拡散層50,53の長さの比βに比
例する数だけN+拡散層51にスリツトを設け、
N+拡散層51,54の横広がりによる相対比の
誤差を除去している。この様子を第5図を参照し
て説明する。
In this application, the resistors R3 and R4 that take the relative ratio are the fourth
As the vectors are indicated by arrows in the figure, the number of N + diffusions is proportional to the ratio β of the lengths of the P-type diffusion layers 50 and 53 of the resistor, which takes the relative ratio of the number of vectors regardless of the order of the direction of the vectors. providing a slit in the layer 51;
Errors in the relative ratio due to the lateral spread of the N + diffusion layers 51 and 54 are removed. This situation will be explained with reference to FIG.

この第5図のピンチ抵抗R3′,R4′は第4図
のピンチ抵抗R3,R4に比し、P型拡散層5
0,53とN+拡散層51,54との重複部分の
数がそれぞれ1つ多くなつているが、以下の説明
に影響を与えるものでない。
The pinch resistances R3' and R4' in FIG. 5 are different from the pinch resistances R3 and R4 in FIG.
Although the number of overlapping parts between 0 and 53 and the N + diffusion layers 51 and 54 is increased by one, this does not affect the following explanation.

また50′,51′,53′,54′はそれぞれ拡
散層50,51,53,54の製造誤差による横
広がり分を示したものである。
Further, 50', 51', 53', and 54' indicate the lateral spread due to manufacturing errors of the diffusion layers 50, 51, 53, and 54, respectively.

ここでピンチ抵抗R3′とピンチ抵抗R4′との
相対比をとると、マスク上でN+拡散層51,5
4がP型拡散層50,53と重複する部分の長さ
は、L=L1′+L2′+L3′+L8=L4′+L5′+L6′+
L7′となり、N+拡散層51,54とP型拡散層5
0,53と重複する部分の数はn=n′=4となつ
ているから相対比は(5)式よりR/R=4ΔL+L
/4ΔL+L=1と なり拡散の横広がりによらず一定で精度良く相対
比がとれる。尚、P型拡散層51と54の幅は等
しいとする(W=W′)。
Here, if we take the relative ratio of the pinch resistance R3' and the pinch resistance R4', we can see that the N + diffusion layers 51, 5 on the mask
The length of the portion where 4 overlaps with the P-type diffusion layers 50 and 53 is L=L 1 ′+L 2 ′+L 3 ′+L 8 =L 4 ′+L 5 ′+L 6 ′+
L 7 ', N + diffusion layers 51, 54 and P type diffusion layer 5
Since the number of overlapping parts with 0 and 53 is n=n'=4, the relative ratio is R 6 /R 5 = 4ΔL+L from equation (5).
/4ΔL+L=1, and a constant and accurate relative ratio can be obtained regardless of the lateral spread of diffusion. It is assumed that the widths of the P-type diffusion layers 51 and 54 are equal (W=W').

本発明の他の実施例を第6図に示す。 Another embodiment of the invention is shown in FIG.

この実施例はピンチ抵抗R5の抵抗値をピンチ
抵抗R6の抵抗値の2倍に設定したもので、ピン
チ抵抗R5,R6はそれぞれN型エピタキシヤル
層に形成されている。ピンチ抵抗R5は直線状の
P型拡散層38と、このP型拡散層38の表面で
6回重複する櫛歯状のN+拡散層39とを有し、
P型拡散層38の両端に電極取出部40を有して
いる。一方、ピンチ抵抗R6は2回折れ曲つたP
型拡散層41を有し、これと表面部で重複する
N+拡散層42とを有し、これらの重複は3ケ所
で行なわれている。P型拡散層41の両端には電
極取り出し部43を有している。
In this embodiment, the resistance value of the pinch resistor R5 is set to twice the resistance value of the pinch resistor R6, and the pinch resistors R5 and R6 are each formed in an N-type epitaxial layer. The pinch resistor R5 has a linear P-type diffusion layer 38 and a comb-shaped N + diffusion layer 39 that overlaps six times on the surface of the P-type diffusion layer 38.
Electrode extraction portions 40 are provided at both ends of the P-type diffusion layer 38. On the other hand, the pinch resistor R6 is a P that is bent twice.
It has a type diffusion layer 41 and overlaps with this at the surface part.
The N + diffusion layer 42 is overlapped at three locations. The P-type diffusion layer 41 has electrode lead-out portions 43 at both ends.

すなわち、この実施例は、マスクレイアウトの
関係でピンチ抵抗R5は縦長の形状をとらねばな
らず、又ピンチ抵抗R6は正方形の形状をとらね
ばならない時のもので、特にこれらの抵抗比を
1:2にすべく、マスク上でP型拡散層38,4
1の長さの比を1:2に設定することを想定した
ものである。
That is, in this embodiment, the pinch resistor R5 must have a vertically elongated shape and the pinch resistor R6 must have a square shape due to the mask layout, and in particular, the ratio of these resistances is set to 1: 2, P-type diffusion layers 38, 4 are formed on the mask.
It is assumed that the length ratio of 1 is set to 1:2.

この場合、抵抗R5,R6の抵抗値をそれぞれ
R5,R6とするとそれらの相対比は(5)式より
/R=n′ΔL+βL/nΔL+L=6ΔL+2
L/3ΔL+L=2 この例でも精度良く相対比がとれる事がわか
る。
In this case, if the resistance values of resistors R5 and R6 are R5 and R6, respectively, their relative ratio is R 5 /R 6 =n'ΔL+βL/nΔL+L=6ΔL+2 from equation (5).
L/3ΔL+L=2 It can be seen that the relative ratio can be obtained with good accuracy in this example as well.

この様に本願によれば、ピンチ抵抗の相対比は
その形状を相似形とする事なく、(5)式でn′=nβ
(βは2つの抵抗のP型拡散層の長さの比例定
数)となる様N+拡散層51,39にスリツトを
設けることで、自由な形状に設定でき、精度良く
相対比がとれる。このため今後の半導体集積回路
の小回路電流化に対して大いに役立つ。
In this way, according to the present application, the relative ratio of the pinch resistance is determined by equation (5), n′=nβ, without making the shapes similar.
By providing slits in the N + diffusion layers 51 and 39 so that β is a proportionality constant of the lengths of the P-type diffusion layers of the two resistors, it is possible to set them to any shape and to obtain a relative ratio with high accuracy. Therefore, it will be of great help in the future miniaturization of circuit current in semiconductor integrated circuits.

N+拡散層51,39のスリツト間隔は拡散領
域の横広がりでスリツトがうまらない程度の間隔
であれば自由に設定できる。
The spacing between the slits in the N + diffusion layers 51 and 39 can be freely set as long as the slits do not fit together due to the lateral expansion of the diffusion region.

上記はP型抵抗にN+型拡散層を形成するピン
チ抵抗について説明したきたが、本願は同様にN
型抵抗にP+型拡散層を形成してなるピンチ抵抗
にも適用される。
The above has explained the pinch resistance in which an N + type diffusion layer is formed in the P type resistance, but this application also describes the
It is also applied to a pinch resistor formed by forming a P + type diffusion layer on a type resistor.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は一般的なピンチ抵抗の断面図、第2図
はその平面図である。第3図はピンチ抵抗を2つ
形成した従来技術を示す平面図である。第4図は
本発明の一実施例を示す平面図である。第5図は
本発明の一実施例の効果を説明するための平面図
である。第6図は本発明の他の実施例を示す平面
図である。 1,12,17,38,41,50,53……
P型拡散層、2,14,19,39,42,5
1,54……N+型拡散層、3……電極、4……
表面酸化膜、5……N型エピタキシヤル層、6…
…P型基板、16,21,40,43,52,5
5……電極取出部。
FIG. 1 is a sectional view of a general pinch resistor, and FIG. 2 is a plan view thereof. FIG. 3 is a plan view showing a conventional technique in which two pinch resistors are formed. FIG. 4 is a plan view showing an embodiment of the present invention. FIG. 5 is a plan view for explaining the effects of one embodiment of the present invention. FIG. 6 is a plan view showing another embodiment of the present invention. 1, 12, 17, 38, 41, 50, 53...
P-type diffusion layer, 2, 14, 19, 39, 42, 5
1,54...N + type diffusion layer, 3...electrode, 4...
Surface oxide film, 5... N-type epitaxial layer, 6...
...P type substrate, 16, 21, 40, 43, 52, 5
5... Electrode extraction part.

Claims (1)

【特許請求の範囲】[Claims] 1 所定の抵抗比を有する第1および第2の抵抗
素子を有する半導体集積回路装置において、前記
第1の抵抗素子は、一導電型の第1の領域とこの
第1の領域に選択的に重複する逆導電型の第2の
領域とを有し、前記第2の抵抗素子は、前記第1
の領域とは異なる形状をもつて形成された前記一
導電型の第3の領域とこの第3の領域に選択的に
重複する前記逆導電型の第4の領域とを有し、前
記抵抗比は前記第1の領域への前記第2の領域の
重複回数と前記第3の領域への前記第4の領域の
重複回数との比に等しいことを特徴とする半導体
集積回路装置。
1. In a semiconductor integrated circuit device having first and second resistance elements having a predetermined resistance ratio, the first resistance element selectively overlaps a first region of one conductivity type and the first region. and a second region of an opposite conductivity type, and the second resistive element has a second region of an opposite conductivity type.
the third region of one conductivity type formed to have a shape different from that of the region; and the fourth region of the opposite conductivity type selectively overlapping with the third region, and the resistance ratio is equal to the ratio of the number of times the second region overlaps with the first region and the number of times the fourth region overlaps with the third region.
JP8040881A 1981-05-27 1981-05-27 Semiconductor integrated circuit device Granted JPS57196558A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP8040881A JPS57196558A (en) 1981-05-27 1981-05-27 Semiconductor integrated circuit device
DE8282104644T DE3273527D1 (en) 1981-05-27 1982-05-27 Semiconductor device having two resistors
EP82104644A EP0066263B2 (en) 1981-05-27 1982-05-27 Semiconductor device having two resistors
US06/867,422 US4725876A (en) 1981-05-27 1986-05-15 Semiconductor device having at least two resistors with high resistance values

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8040881A JPS57196558A (en) 1981-05-27 1981-05-27 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS57196558A JPS57196558A (en) 1982-12-02
JPS6256666B2 true JPS6256666B2 (en) 1987-11-26

Family

ID=13717459

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8040881A Granted JPS57196558A (en) 1981-05-27 1981-05-27 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS57196558A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62163359A (en) * 1986-01-14 1987-07-20 Sanyo Electric Co Ltd Semiconductor resistance device
JP5072396B2 (en) * 2006-06-12 2012-11-14 株式会社リコー Resistance element adjustment method, resistance element whose resistance value and temperature dependency characteristics are adjusted by the resistance element adjustment method, and current generator using the resistance element
JP7027176B2 (en) * 2018-01-22 2022-03-01 ラピスセミコンダクタ株式会社 Semiconductor device

Also Published As

Publication number Publication date
JPS57196558A (en) 1982-12-02

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