JP3242272B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device suitably implemented in a semiconductor integrated circuit having a multi-layer wiring structure, and more particularly, to a structure in which a plurality of transistors are integrated to control a relatively large current. The present invention relates to a semiconductor device having a built-in power transistor.

[0002]

2. Description of the Related Art In semiconductor integrated circuits, it is necessary to improve the degree of integration with the advancement of functions, and it is becoming common to use a multilayer wiring structure. In a semiconductor integrated circuit having a built-in light receiving element, a circuit portion is generally shielded from light to prevent the influence of light, and a multi-layer wiring structure is often used for that purpose. Many semiconductor integrated circuits with a built-in light receiving element have a built-in power transistor capable of handling a large current.

A semiconductor integrated circuit is formed on a semiconductor substrate, and the amount of current that can flow per transistor is limited due to the limitation of being formed on a semiconductor substrate. I can make it flow.

FIG. 16 is a perspective view showing a cross section of a typical conventional semiconductor device 61, FIG. 17 is a plan view of the semiconductor device 61, and FIG. 18 is a sectional line III-III in FIG. 19 is a cross-sectional view taken along line IV-IV in FIG. Further, an insulating film 80 and a protective film 82 described later are omitted.

FIGS. 18 and 19 are cross-sectional views of two transistor rows formed in the semiconductor device 61 shown on the left side of FIG. 17, and the other transistor rows are omitted because they have the same structure. .

The semiconductor device 61 is formed by forming a plurality of layers of metal film wiring and an insulating film between the respective layers on a semiconductor substrate 63 formed as described later.

A semiconductor substrate 63 is formed on a p-type semiconductor substrate 71 by diffusing an impurity such as antimony into an n-type buried diffusion layer 72 in a region set in advance to form a transistor row. Buried diffusion layer 72
N-type epitaxial layer 7 on p-type semiconductor substrate 71 containing
3 is formed by growing. Further, an impurity such as boron is diffused in a region surrounding the n-type epitaxial
A mold separation / diffusion layer 74 is formed.

The n-type collector compensation diffusion layer 75 forming the collector region of the transistor in the semiconductor device 61
An impurity such as phosphorus is n-type buried diffusion layer 72 in a predetermined region.
Is formed by diffusing to a depth that reaches. The n-type collector compensation diffusion layer 75 is formed in a comb shape in plan view.

The p-type base diffusion layer 76 constituting the base region of the transistor is formed by diffusing an impurity such as boron into a region between the n-type collector compensation diffusion layers 75 formed in a comb shape. Is done.

Further, the n-type emitter diffusion layer 77 serving as an emitter region of the transistor is provided with the p-type base diffusion layer 7.
6 is formed by diffusing impurities such as phosphorus into a specific region. The n-type emitter diffusion layer 77 has a constant n-type emitter diffusion layer portion 77a as shown in FIG. 18 and a divided n-type emitter diffusion layer portion 77b as shown in FIG. Are formed alternately and repeatedly at intervals of.

An n-type collector compensation diffusion layer 75, a p-type base diffusion layer 76,
After the n-type emitter diffusion layer 77 is formed, an oxide film 78 is formed on the surface of the semiconductor substrate 63. The oxide film 78 has an emitter contact 83 serving as a contact window for electrically connecting a first-layer wiring 79 to be described later to each element region of the transistor formed on the semiconductor substrate 63, a base contact 84, and a collector. A contact 85 is formed.

After the oxide film 78 is formed, a first layer wiring 79 is formed by using an evaporation method or the like. Aluminum or the like is used as a material of the first layer wiring 79. The first-layer wiring 79 includes a first-layer base wiring portion 67, a first-layer emitter wiring portion 68, and a first-layer collector wiring portion 69. The first-layer base wiring portion 67 is electrically connected to the p-type base diffusion layer 76 via the base contact 84, and the first-layer emitter wiring portion 68 is connected to the n-type emitter diffusion layer portion 77 via the emitter contact 83.
a, 77b, and the first-layer collector wiring portion 69 is electrically connected to an n-type collector compensation diffusion layer 75 via a collector contact 85.

After forming the first layer wiring 79, an insulating film 80 is formed so as to cover the first layer wiring 79. The insulating film 80 electrically insulates the first-layer wiring 79 from a second-layer wiring 91 described later. As shown in FIG. 18, a through hole 87 for a collector and a through hole 88 for an emitter, which are contact windows, are formed in the insulating film 80 to electrically connect the first-layer wiring 79 and the second-layer wiring 91. The collector through hole 87
An emitter through hole 88 is formed at a position sandwiched by the collector contact 85, and an emitter through hole 88 is formed at a position sandwiched by the emitter contact 83.

Next, a second-layer wiring 91 is formed by an evaporation method or the like so as to cover the insulating film 80. Aluminum or the like is used as a material of the second-layer wiring 91. The second-layer wiring 91 includes a second-layer emitter wiring portion 81 and a second-layer collector wiring portion 70. The second-layer emitter wiring portion 81 is electrically connected to the first-layer emitter wiring portion 68 through an emitter through hole 88, and
The first-layer collector wiring portion 70 is electrically connected to the first-layer collector wiring portion 69 via a through hole 87 for collector.

After the second-layer wiring portion 91 is formed, a protective film 82 for protecting the wiring and the like is formed. Second layer wiring 9
Numeral 1 is also used to shield the circuit portion, and even when the light receiving element is installed in the semiconductor device 61, it is possible to prevent the light receiving element from malfunctioning due to the light applied to the circuit portion.

In the semiconductor device 61 configured as described above, the emitter pad 89 and the collector pad 90 for supplying a current to each transistor row are often provided on the same side of the semiconductor substrate 63. Wiring is routed and connected from 90 to each transistor, so that the resistance of the wiring connected to each transistor row varies, and the ratio of the values of the flowing currents becomes uneven.

Therefore, the balance resistor 16 is connected to the base of the transistor so as to reduce the variation in the value of the current flowing in each transistor row, that is, to expand the safe operation area.

Japanese Patent Application Laid-Open No. 5-29 discloses a technique for increasing the amount of current that can be passed through a semiconductor device by forming a metal film wiring formed when forming a semiconductor device into a multilayer structure.
No. 320 is disclosed. According to the above publication, the metal film wiring in a portion where a large current is to flow is made to have a multilayer structure to increase the cross-sectional area of the wiring so that even if a large current flows, the disconnection of the wiring due to electromigration does not occur. I have.

Japanese Unexamined Patent Publication (Kokai) No. 2-272741 discloses a technique for expanding the safe operation area by changing the shape of the emitter electrode. According to the above publication, a base electrode is provided on a base region formed on a semiconductor substrate so as to sew between a plurality of emitter regions, the base electrode is covered with an insulating film, and the base electrode is provided on the plurality of emitter regions. And an emitter electrode disposed on the insulating film. As a result, the distance between each emitter region and the base electrode is reduced, the concentration of current at the emitter edge is reduced, and the safe operation region is expanded.

FIG. 20 is an equivalent circuit diagram of the semiconductor device 61. In FIG. 20, each of the transistor rows is represented by transistors 93 to 96, respectively. A balance resistor 16 is connected to each base B of each of the transistors 93 to 96. The resistance of the wiring also enters the emitter E and the collector C, but the resistance on the collector side is not shown because it can be ignored for the operation of the transistor. Resistance entering the emitter side affects the operating point V _be even slightly, to generate a variation in the value of the current flowing in each transistor 93-96.

In order to calculate the wiring resistance of the emitter in each transistor row of the semiconductor device 61, the wiring patterns of the first-layer emitter wiring portion 68 and the second-layer emitter wiring portion 81 are shown in FIG. In FIG. 21, the region indicated by the diagonally upward slant line is a region where only the second-layer emitter wiring portion 81 exists, and the other regions include the first-layer emitter wiring portion 68 and the second-layer emitter wiring portion. 81 are laminated.

In FIG. 21, regions R4, R5, R
6. Calculate the resistance of each region. The region R4 is a rectangular region from the emitter pad 89 on each emitter wiring to the end opposite to the position where the emitter pad 89 is located. The length w12 of the region R4 in the long side direction is 400 μm
And the length w9 in the short side direction is 150 μm. The region R5 is formed on the emitter pad 89 on each emitter wiring.
Is a rectangular area located at the end opposite to the side where is located and adjacent to the region R4 up to the first column and second layer emitter wiring portion 81a. In the region R5, the length w11 of the side contacting the region R4 is 70 μm, and the length w8 of the other side is 80 μm.

The region R6 is a region adjacent to the region R5, and is divided into three regions R7, R8 and R9.
In the region R6, the region R7 and the region R8 are located on the side in contact with the region R5, and the region R9 is located on the other side. The length w11 of the region R6 in the long side direction in contact with the region R5 is 70 μm.
m. The length in the short side direction is 60 μm, which is the sum of 30 μm of the length w6 in the short side direction of the region R9 and 30 μm of the length w7 of one side of the region R7. The region R8 is located on the end side in contact with the region R5 in the first column and second layer emitter wiring portion 81a. In the region R8, the length w13 in the long side direction in contact with the region R5 is 40 μm.
And the short side direction is the same as the length w7 of one side of the region R7. In the region R7, the length w7 of one side is 30 μm, and the length w10 of the other side is 30 μm. As described above, in the region R9, the length w11 in the long side direction is 70 μm, and the length w6 in the short side direction is 3 μm.
0 μm.

Aluminum generally used for wiring is
Since the resistivity is 2.7 × 10 ⁻⁶ Ωcm, if the thickness of the aluminum formed as the wiring is 1.5 μm, the resistance values of the respective regions R4 and R5 are as follows.

R4 = (2.7 × w12 / 2 × 1.5 × w9) × 10 ⁻² = (2.7 × 400/2 × 1.5 × 150) × 10 ⁻² = 24 mΩ R5 = (2 0.7 × w8 / 2 × 1.5 × w11) × 10 ⁻² = (2.7 × 80/2 × 1.5 × 70) × 10 ⁻² = 10 mΩ Further, regarding the resistance value of the region R6, first, Region R7, R
8. Find the resistance value of R9.

R7 = (2.7 × w7 / 2 × 1.5 × w10) × 10 ⁻² = (2.7 × 30/2 × 1.5 × 30) × 10 ⁻² = 9 mΩ R8 = (2 0.7 × w7 / 2 × 1.5 × w13) × 10 ⁻² = (2.7 × 30/2 × 1.5 × 40) × 10 ⁻² = 14 mΩ R9 = (2.7 × w6 / 2 ×) 1.5 × w11) × 10 ⁻² = (2.7 × 30/2 × 1.5 × 70) × 10 ⁻² = 4 mΩ In the region R6, since the regions R7 and R8 are in parallel, R6 = R7 × R8 / (R7 + R8) + R9 = 9 × 14 / (9 + 14) + 4 = 9 mΩ The resistance value of each of the regions R4, R5, and R6 is roughly calculated as follows.

The emitter resistance r5 of the transistor in the first column
R5 = R4 + (R5 + R6) × 1 = 43 mΩ The emitter resistance r6 of the transistor in the second column is r6 = R4 + (R5 + R6) × 2 = 62 mΩ The emitter resistance r7 of the transistor in the third column is r7 = R4 + (R5 + R6) × 3 = 81 mΩ The emitter resistance r8 of the transistor in the fourth column is r8 = R4 + (R5 + R6) × 4 = 100 mΩ, and the difference between the emitter resistances r5 and r8 is 57 mΩ.

Assuming that a current of 1 A flows through the semiconductor device 61, about 0.25 is applied to each transistor row.
A current flows. Assuming that 0.25 A flows in each transistor row, a potential difference from the emitter pad 19 to the emitter portion of each transistor row is obtained. Since regions R5 and R6 exist to connect the respective transistor rows, the transistors in the second and subsequent columns are obtained by multiplying the current flowing in the regions R5 and R6 by the resistance values of the regions R5 and R6 and the transistors in the front row. Is the potential difference up to the emitter of the transistor in the desired column. Therefore, the potential difference up to the emitter of the transistor in the first column is: r5 × 1 (A) = 43 mV The potential difference up to the emitter of the transistor in the second column is: 43+ (R5 + R6) × 0.75 (A) = 57 mV The potential difference up to the emitter of the transistor is 57+ (R5 + R6) × 0.5 (A) = 67 mV The potential difference up to the emitter of the transistor in the fourth column is 67+ (R5 + R6) × 0.25 (A) = 72 mV , A difference occurs in the current flowing according to the difference in the base-emitter voltage. The ratio is expressed as I / I ₀ = exp (qV / kT) (1). In the formula (1), q is an electron charge,
V is the potential difference up to the emitter of each transistor row,
k is Boltzmann's constant and T is absolute temperature.

FIG. 1 shows the ratio of the current flowing through each transistor row.
3 is shown in the graph. The value of the current flowing in the second column is greatly reduced with respect to the value of the current flowing in the first column, and continues to decrease to the third column and the fourth column. It is about 0.3 times the value of the flowing current.

FIG. 22 shows another conventional semiconductor device 1.
It is the perspective view which showed the cross section of 00. Semiconductor device 100
Is similar to the semiconductor device 61 described above.
8 is formed by forming a plurality of metal film wirings and an insulating film between the respective layers.

Assuming that semiconductor device 100 is formed of, for example, a P-channel MOS (Metal Oxide Semiconductor) transistor, semiconductor substrate 108 is formed by diffusing impurities such as boron into n-type semiconductor substrate 101 to be perpendicular to the cross section. The source diffusion layer 103 and the drain diffusion layer 104 are formed so as to form a row.

After forming a diffusion layer to be an element of each MOS transistor, an oxide film 102 is formed on the surface of the semiconductor substrate 108. A contact is formed at a predetermined position in the oxide film 102, and a source wiring 106 and a drain wiring 107 described later are directly connected to the semiconductor substrate 108 by the contact. A source wiring 106 is formed so as to be commonly connected to two adjacent source diffusion layers 103 and to have a comb shape. A column-shaped drain wiring 107 is formed between each column of the source wiring 106 and on one end 108a side of the semiconductor substrate 108 so as to be connected to the drain diffusion layer 104. Source wiring 1
Gate wirings 105 are formed in a row between oxide film 06 and drain wiring 107 via oxide film 102. Source wiring 1
06 and the drain wiring 107 are each formed over two layers.

In the semiconductor device 100, similarly to the above-described semiconductor device 61, the ratio of the values of the currents flowing through the respective MOS transistor columns is not uniform due to the variation in the wiring resistance of the respective MOS transistor columns due to the wiring routing. In each MOS transistor column, the current ratio of each column when the source potential rises due to the wiring resistance is I ₁ / I ₀ = ｛g, where the gate-source voltages of each MOS transistor column are V ₀ and V _{1. ^{m (V 1 -V T) 2}} /2} / {g m (V 0 -V T) 2/2} = {(V 1 -V T) / (V 0 -V T)} 2 ... (2) It is represented by (2) In the equation, g _m is the transconductance, V _T is the threshold voltage.

[0034]

As described above, in the semiconductor device 61 according to the prior art, the current tends to concentrate on the transistor row near the emitter pad 89.
That is, as the distance from the emitter pad 89 increases, the current flowing through each transistor row greatly decreases. Therefore, the balance of the current flowing in each transistor row is poor, and the safe operation area of the semiconductor device 61 cannot be sufficiently widened, and the current that can be handled is small.

Further, the above-mentioned Japanese Patent Laid-Open Publication No.
In the semiconductor device disclosed in the above publication, the collector electrode is provided on the surface opposite to the other electrode, and the structure is different from the semiconductor device according to the present invention. Further, the object of the present invention is to reduce the pinch-in effect by reducing the base spreading resistance, which is different from the object of the present invention.

An object of the present invention is to reduce the variation in wiring resistance of each transistor formed by combining a plurality of transistors on a semiconductor substrate in order to handle a large current, to balance the current flowing through each transistor, An object of the present invention is to provide a semiconductor device having a large operation area.

[0037]

According to the present invention, a plurality of transistors, each having a first emitter wiring, a base wiring, and a first collector wiring formed on a semiconductor substrate, are arranged in a row. In a semiconductor device in which the base wiring, the first collector wiring, and the first emitter wiring of each transistor are commonly connected, the first emitter wiring of each transistor is formed so as to cover each transistor. A first collector wiring commonly connected by the second emitter wiring and covered by the second first emitter wiring is wider than a first collector wiring not covered by the second emitter wiring. It is characterized in that a second collector wiring is laminated on the first collector wiring formed and not covered by the second emitter wiring. Which is a semiconductor device to be. The present invention also provides an emitter region, a base region,
And a plurality of transistors arranged adjacent to each other and formed in a row with a plurality of transistors formed by forming a collector region, and forming a base line, a collector region, and an emitter region of each transistor line in a common base wiring. ,
In the semiconductor device connected to the first collector wiring and the first emitter wiring, the first emitter wiring of each transistor row is shared by a second emitter wiring formed so as to cover the plurality of transistor rows. The first collector wiring connected and covered by the second emitter wiring is formed wider than the first collector wiring not covered by the second emitter wiring, and
A second collector wiring is formed on the first collector wiring not covered by the emitter wiring. Further, the present invention is characterized in that an emitter pad and a collector pad for supplying a current to each of the transistor rows via the first emitter wiring and the first collector wiring are provided on the same side of the semiconductor substrate. Also, in the present invention, the first emitter wiring and the first collector wiring are formed in a comb shape,
The invention is characterized in that the first emitter wiring and the first collector wiring are engaged with each other. Further, in the invention, it is preferable that the second collector wiring is formed on the first collector wiring, which is not covered with the second emitter wiring, on a contact portion with the collector region. . Further, according to the present invention, on a semiconductor substrate, a plurality of transistors are formed in which a plurality of transistors each having a source region, a gate region, and a drain region formed adjacent to each other are arranged in a row. In a semiconductor device in which a gate region, a drain region, and a source region of a column are connected to a common gate line, a first drain line, and a first source line, respectively, the first source line of each transistor column is A first drain wiring, which is commonly connected by a second source wiring formed to cover the transistor row and is covered by the second source wiring, is a first drain wiring which is not covered by the second source wiring. A first drain wiring formed wider than the drain wiring and not covered by the second source wiring has a drain region On the contact part is a semiconductor device in which the second drain wiring is characterized in that it is formed by laminating.

[0038]

According to the present invention, a semiconductor device includes a first emitter wiring, a base wiring, and a first wiring formed on a semiconductor substrate.
A plurality of bipolar transistors each of which is composed of a collector wiring and a collector wiring, and a base wiring, a first collector wiring, and a first emitter wiring of each transistor are commonly connected, and a second emitter A wiring is formed so as to cover each transistor, and a first emitter wiring of each transistor is commonly connected. The semiconductor device is configured by combining a plurality of transistors so that a large current can be handled, so that current flows evenly through each transistor. Therefore, since the second emitter wiring is formed so as to cover a region set in advance so as to form a transistor row, since the wiring to each transistor is not routed, the resistance of the emitter wiring becomes sufficiently small, Variations in the resistance of the emitter wiring for each transistor are also reduced. Since the variation in the resistance of the emitter wiring of each transistor is reduced, current can flow evenly through each transistor.

Further, the first collector wiring covered by the second emitter wiring is formed wider than the first collector wiring not covered by the second emitter wiring. Therefore, the first collector wiring covered by the second emitter wiring has a larger cross-sectional area per layer than the first collector wiring not covered by the second emitter wiring.

Further, a second collector wiring is formed on the first collector wiring not covered by the second emitter wiring. Therefore, the second collector wiring is formed so as to overlap the first collector wiring not covered by the second emitter wiring, and the cross-sectional area of the collector wiring is increased. By increasing the cross-sectional area of the wiring, the problem of wiring disconnection due to electromigration is eliminated, and the reliability of the semiconductor device is improved.

Further, according to the present invention, a semiconductor device comprises a plurality of unipolar transistors each having a first source wiring, a gate wiring, and a first drain wiring formed on a semiconductor substrate. And the gate wiring, the first drain wiring, and the first source wiring of each transistor are connected in common, and the second source wiring is formed so as to cover each transistor, and the first source of each transistor is formed. Connect the wiring in common. Therefore, as in the case where a bipolar transistor is formed in a semiconductor device, variation in the resistance of the source wiring of each transistor is reduced, and current can flow evenly through each transistor.

[0042]

FIG. 1 is a perspective view showing a cross section so that the layer structure of a semiconductor device 31 according to a first embodiment of the present invention can be understood. Note that an insulating film 10 and a protective film 12, which will be described later, are not shown. In the semiconductor device 31, transistor rows 41a to 41d are formed in which an emitter wiring, a base wiring, and a collector wiring are commonly connected and arranged in a column in a direction perpendicular to the cross section.

The transistor array 41a includes a first base wiring portion 32, first emitter wiring portions 33a and 33b, and a first collector wiring portion 35a made of aluminum or the like on a semiconductor substrate 21 formed as described later. ,
35b, the second-layer emitter wiring 11, and the second-layer collector wiring 37 are formed by wiring. First-layer base wiring portion 32, first-layer emitter wiring portions 33a, 33
b and the first-layer collector wiring portions 35a and 35b
It is included in the first-layer wiring 9. An insulating film 10 described later is formed between the first-layer wiring and the second-layer wiring, and is electrically connected only at an arbitrary position.

In the semiconductor device 31, the second-layer emitter wiring 11 is formed so as to substantially cover the semiconductor substrate 21. The first-layer collector wiring portion 35b covered with the second-layer emitter wiring 11 is formed wider than the other first-layer wirings, thereby preventing the cross-sectional area from being reduced. Since the first-layer collector wiring portion 35a formed on the one side portion 21a side on the semiconductor substrate 21 is not covered with the second-layer emitter wiring 11, the second-layer collector wiring 37 is formed by laminating the wiring. The cross-sectional area becomes wider. The first-layer collector wiring portion 35b is shared with the transistor row 41b formed adjacent to the transistor row 41a.

FIG. 2 is a plan view of the semiconductor device 31, FIG. 3 is a cross-sectional view taken along the solid line II of FIG. 2, and FIG. 4 is a cross-sectional line II-II of FIG. 3 is a cross-sectional view as viewed from a solid line portion of FIG. In the vicinity of corners 31b and 31c on one end 31a side of semiconductor device 31 shown in FIG.
Are formed. A current is supplied to the semiconductor device 31 via the emitter pad 19 and the collector pad 20.

On the opposite side of the one end 31a of the semiconductor device 31, a balance resistor 16 connected to the base of each transistor row is formed. The balance resistor 16 is connected to one side 21 of the semiconductor substrate 21 forming the semiconductor device 31.
The transistors are arranged from the side a so as to correspond to the respective transistor rows.

Semiconductor substrate 21 constituting semiconductor device 31
As shown in FIG. 5, an n-type buried diffusion layer 2 is formed in a rectangular shape by diffusing impurities such as antimony in a predetermined region where each transistor is to be formed on a p-type semiconductor substrate 1 as shown in FIG. . Further, on one side 1a of the p-type semiconductor substrate 1, four rectangular n-type buried diffusion layers 2a whose longitudinal direction is orthogonal to the longitudinal direction of the n-type buried diffusion layer 2 are formed. .

An n-type epitaxial layer 3 is formed on a p-type semiconductor substrate 1 by growing. n-type epitaxial layer 3
Is formed so as to cover the n-type buried diffusion layer 2 as shown in FIGS. 3 and 4, and is formed on the p-type semiconductor substrate 1 outside the n-type buried diffusion layer 2. The n-type epitaxial layer portion 3 covers the n-type buried diffusion layer portion 2a.
a is formed.

Thereafter, as shown in FIG. 5, an impurity such as boron is diffused outside the element forming region of the n-type epitaxial layer 3 formed on the p-type semiconductor substrate 1 to form a p-type isolation / diffusion layer 4. Is done. By forming the p-type separation / diffusion layer 4, each layer configured as described above can be electrically separated.

On the semiconductor substrate 21 on which the respective layers are formed as shown in FIG. 5, regions to be elements of transistors are formed as shown in FIG. In FIG. 6, a layer that has already been formed is indicated by a two-dot chain line.

The p-type base diffusion layer 6 constituting the base region of the transistor is formed by diffusing impurities such as boron into a region on the n-type buried diffusion layer 2.
Next, an impurity such as phosphorus is diffused between the p-type base diffusion layers 6 so as to be in a comb-like shape without contacting each other to form an n-type collector compensation diffusion layer 5 constituting a collector region of the transistor. I do. The n-type collector compensation diffusion layer 5 is formed to a depth reaching the n-type buried diffusion layer 2 as shown in FIGS.

N constituting the emitter region of the transistor
The type emitter diffusion layer 7 is formed by diffusing impurities such as phosphorus in a region indicated by oblique lines rising to the right in FIG. The region indicated by the diagonal lines is formed to be slightly smaller than the p-type base diffusion layer 6 described above, and a plurality of regions (8 in this embodiment) are formed in the central portion of the region in the longitudinal direction.
Are formed in a row. Through hole 9
In FIG. 8, the n-type emitter diffusion layer 7 is not formed, and the p-type base diffusion layer 6 is exposed. The n-type emitter diffusion layer portion 7a is formed by diffusing impurities into a layer above the n-type epitaxial layer portion 3a so as to have the same size as the region of the n-type buried diffusion layer portion 2a. You.

Wiring is performed in the element region of each transistor on the semiconductor substrate 21 configured as described above. In addition,
The following description will be made mainly for the transistor row 41a. However, since the structure of the transistor rows 41a to 41d is substantially the same, the same applies to the other transistor rows 41b to 41d. First, as shown in FIGS. 3, 4, and 8, an oxide film 8 of silicon oxide or the like is formed on the surface of the semiconductor substrate 21. In FIG. 8, each region already formed on the semiconductor substrate 21 is indicated by a two-dot chain line.

The oxide film 8 is formed with a plurality of openings for electrically connecting a metal film wiring described later and the semiconductor substrate 21. A metal, which is a material of the metal film wiring, enters each of the openings, and electrically connects the element region of each transistor formed on the semiconductor substrate 21 to the metal film wiring. Each opening becomes an emitter contact 13, a base contact 14, and a collector contact 15 depending on the position where each opening is formed.

The base contact 14 is formed in a rectangular shape at the center of each through hole 98 described above. The emitter contacts 13 are formed in two rows in the region that is the n-type emitter diffusion layer 7, are located at both ends with the base contact 14 interposed therebetween, and are formed at predetermined intervals in a plurality. The collector contact 1
Numeral 5 is formed in a region on the n-type collector compensation diffusion layer 5, and a first collector contact 15 a is formed in a rectangular shape and slightly smaller than the region between the n-type emitter diffusion layers 7. . In a region not sandwiched between the n-type emitter diffusion layers 7, a second collector contact 15b having a rectangular shape, the same length as the emitter contact 13, and the same interval is formed. Further, a rectangular third collector contact 1 is formed in the region on the short side of the n-type emitter diffusion layer 7 so that the long side of the n-type emitter diffusion layer 7 is orthogonal to its own longitudinal direction.
5c is formed. Further, the n-type collector compensation diffusion layer 5
In the vicinity of the corner 5a, a rectangular fourth collector contact 15d is formed. Resistive contacts 99 are formed at both longitudinal ends of the n-type emitter diffusion layer portion 7a.

A first layer wiring 9 is formed as shown in FIG. 9 so as to cover the oxide film 8 formed as shown in FIG. The first layer wiring 9 is constituted by the following four regions. 1
The layer emitter wiring 9a is formed in a region that covers all the emitter contacts 15 formed on the semiconductor substrate 21 in common. The first-layer collector wiring 9b is formed in a region that covers all the collector contacts 15 in common. The first-layer base wiring 9c is electrically connected to each base contact 14 for each transistor row, and further electrically connected to one-side resistance contact 99a. The resistance contacts 99b on the other side are electrically connected in common by the first-layer emitter wiring 9d. The first-layer emitter wiring 9a includes a first-layer emitter wiring portion 33 constituting the transistor row 41,
The first-layer collector wiring 9b includes a first-layer collector wiring part 35 forming the transistor row 41, and the first-layer base wiring 9c includes a first-layer base wiring part 32 forming the transistor row 41. .

The first-layer wiring 9 is inserted into the emitter contact 13, the base contact 14, the collector contact 15, and the resistance contact 99 shown by a two-dot chain line in FIG. The respective regions and the first-layer wiring 9 are electrically connected as shown in FIG.

The first-layer wiring 9 is formed by depositing aluminum or the like on the surface of the semiconductor substrate 21 on which the oxide film 8 is formed by vapor deposition or the like so as to form a wiring of a metal film. That is, the semiconductor substrate 21 is arranged in a vacuum, a metal source to be vapor-deposited is arranged so as to face the semiconductor substrate 21, and the metal is evaporated by irradiating an electron beam to be deposited on the semiconductor substrate 21. . The first-layer wiring 9 is formed by a sputtering method other than the vapor deposition method or a CVD (Chemical Vapou).
r Deposition) method. After the formation of the metal film, the metal film other than the desired portion is removed by corrosion.

An insulating film 10 for electrically insulating the first-layer wiring 9 and a later-described second-layer wiring is formed so as to cover all of the first-layer wiring 9 formed as described above. As shown in FIG. 3, FIG. 4 and FIG.
A through hole 17 for a collector, which is a through hole for electrically connecting the layer wiring 9 and the wiring formed in the second layer,
The through hole 18 for the emitter, the hole 45 for the emitter pad, and the hole 46 for the collector pad are formed in a region other than the region.

The collector through hole 17 is formed in the third direction shown in FIG. 8 with respect to the longitudinal direction of the first-layer collector wiring 9b.
The collector contact 15c is formed at a position sandwiching the collector contact 15c, and each second collector contact 15
b and the fourth collector contact 15d. The through hole 18 for the emitter is 1
It is formed on the layer emitter wiring 9a at a position sandwiched in the longitudinal direction by the emitter contact 13 shown in FIG. An emitter pad hole 45 is formed near the corner 31b of the semiconductor device 31 on the first layer emitter wiring 9a. Hole 4 for collector pad
6 is formed near the corner 31c of the semiconductor device 31 on the first layer emitter wiring 9a.

After forming the insulating film 10, a second-layer metal film wiring is formed again by the vapor deposition method or the like. The second-layer metal film wiring is formed in a region surrounded by a solid line in FIG. The second-layer emitter wiring 11 includes a first-layer emitter wiring 9a for commonly connecting the emitters of the respective transistor rows 41, and a first-layer base wiring 9c for commonly connecting the bases of the respective transistor rows to the respective transistor rows.
And the region of the first-layer collector wiring 9b sandwiched between the first-layer emitter wirings 9a and the hole 45 for the emitter pad are formed in a rectangular shape. The second layer collector wiring 37 is the first layer collector wiring 9.
An L-shape is formed so as to cover all of the collector through hole 17 and the collector pad hole 46 on b.
Each of the holes 17, 18, 4 formed in the insulating film 10
5, 46 are indicated by two-dot chain lines. As shown in FIG. 3, the first and second wiring layers are electrically connected to each other through through holes 17 and 18 provided in the insulating film 10.

After the second-layer wirings 11 and 37 are formed,
A protective film 12 for protecting wirings and the like is formed so as to cover the entire semiconductor substrate 21.

In the semiconductor device 31 configured as described above, the resistance value of the emitter wiring is examined. FIG. 12 shows the first-layer emitter wiring 9a and the second-layer emitter wiring 11 in the semiconductor device 31 in a superimposed manner, and only the second-layer emitter wiring 11 is present in a region shown by oblique lines rising to the right. The other region is a region formed by laminating the second-layer emitter wiring 11 on the first-layer emitter wiring 9a.

In FIG. 12, since it is considered that little current flows in the common wiring portion on the other side where the emitter pad 19 is located for each transistor, regions R1 and R2 indicated by broken lines in FIG. , R3, and the resistance of the emitter wiring is roughly estimated.

The region R1 is a rectangular region from the emitter pad 19 to the common wiring portion on the emitter wiring. The length w1 of the region R1 in the long side direction is 330 μm.
m, and the length w3 in the short side direction is 150 μm. The region R2 is a region where only the second-layer emitter wiring 11 whose long side is in contact with the region R1 exists. In the region R2, the length w2 in the long side direction in contact with the region R1 is 300 μm, and the length w4 in the short side direction is 90 μm. Region R3
Is a region where the long side is in contact with the region R2 and becomes the emitter wiring of the first transistor column. In the region R3, the length in the long side direction in contact with the region R2 is the same, and the length w5 in the short side direction is 90 μm. Further, the region R3 is divided into three so as to be parallel to the long side, and the length w6 in the short side direction of the two regions existing across the region where only the center second-layer emitter wiring 11 exists is sandwiched. Is 30 μm.

Generally, the resistivity of aluminum used for wiring is 2.7 × 10 ⁻⁶ Ωcm, and if the thickness of aluminum formed as wiring is 1.5 μm, the resistance of each region R1, R2, R3 The values are as follows:

R1 = (2.7 × w1 / 2 × 1.5 × w3) × 10 ⁻² = (2.7 × 330/2 × 1.5 × 150) × 10 ⁻² = 20 mΩ R2 = (2 0.7 × w4 / 1.5 × w2) × 10 ⁻² = (2.7 × 90 / 1.5 × 300) × 10 ⁻² = 5 mΩ R3 = (2.7 × w6 / 2 × 1.5 ×) w2) × 10 ⁻² × 2 + (2.7 × (w5-2 × w6) /1.5×w2) × 10 ⁻² = (2.7 × 30/2 × 1.5 × 300) × 10 ⁻² × 2 + (2.7 × 30 / 1.5 × 300) × 10 ⁻² = 4 mΩ The value of the emitter resistance in each transistor row is determined from the values of the regions R1, R2, and R3.

The emitter resistance of the transistor in the first column is r1 = R1 + R2 + R3 = 29 mΩ The emitter resistance of the transistor in the second column is r2 = R1 + R2 + R3 + R2 + R3 = 38 mΩ The emitter resistance of the transistor in the third column is r3 = R1 + (R2 + R3) × 3 = 47 mΩ The emitter resistance of the transistor in the fourth row is r4 = R1 + (R2 + R3) × 4 = 56 mΩ, the difference between the emitter resistances r1 and r4 is 27 mΩ, and the variation in the value of the emitter resistance of each transistor row is as described above. It became smaller than the conventional example.

Assuming that a current of 1 A flows through the semiconductor device 31, a current of about 0.25 A flows through each transistor row. Assuming that 0.25 A flows through each transistor row, a potential difference from the emitter pad 19 to the emitter portion of each transistor row is determined. Since the regions R2 and R3 exist between the respective transistor rows, after the transistors in the second column, the current flowing in the regions R2 and R3 is multiplied by the resistance value of the regions R2 and R3, and the current in the front row is multiplied. The sum of the potential differences to the emitters of the transistors is the potential difference to the emitters of the transistors in the desired column.
Therefore, the potential difference up to the emitter of the transistor in the first column is: r1 × 1 (A) = 29 mV The potential difference up to the emitter of the transistor in the second column is: 29+ (R2 + R3) × 0.75 (A) = 36 mV The potential difference up to the emitter of the transistor No. is 36+ (R2 + R3) × 0.5 (A) = 41 mV The potential difference up to the emitter of the transistor in the fourth column is 41+ (R2 + R3) × 0.25 (A) = 43 mV. The ratio of the current flowing through each transistor row was calculated using the above-described equation (1), and is shown in the graph of FIG. Compared with the result in the conventional example, the variation in the current ratio flowing for each transistor row is reduced.

As described above, in this embodiment, the second-layer emitter wiring 11 is connected to the first-layer emitter wiring 9a via the emitter through hole 18 so as to partially extend over the first-layer collector wiring 9b. Since all connections are made to the emitters of the transistor rows, the change in the emitter wiring resistance for each transistor row is reduced, the difference in current flowing through each transistor row can be reduced, and the safe operation area can be widened. .

In the present embodiment, the first-layer collector wiring 9b covered with the second-layer emitter wiring 11 is formed with the width of the wiring being wider than the other wirings. , The cross-sectional area can be increased.

Further, in this embodiment, the first-layer collector wiring portion 3 not covered by the second-layer emitter wiring 11
At 0a, the second-layer collector wiring 37 is formed.
The cross-sectional area can be increased without increasing the width of the wiring, and the size of the substrate can be reduced.

FIG. 14 is a plan view of a semiconductor device 51 according to a second embodiment of the present invention. In the semiconductor device 51 according to the present embodiment, the semiconductor device 3 according to the above-described embodiment is used.
The same components as those in 1 are denoted by the same reference numerals and description thereof is omitted.

A feature of the semiconductor device 51 of this embodiment is that an opening for electrically connecting a base region of each transistor formed in a row on the semiconductor substrate 21 to a wiring formed in the first layer. Base contact 5
2 and the emitter region 200 are formed in a band shape. That is, in the semiconductor device 51, the base region of each transistor on the semiconductor substrate 21 is
The base wiring 9c is in linear contact with the layer base wiring 9c, and the emitter region 200 is formed at both ends of a region obtained by dividing each base region formed by the p-type base diffusion layer 6 into three in the long side direction. .

The other structure and the manufacturing method of the semiconductor device 51 are the same as those of the semiconductor device 31 described in the first embodiment, and the description is omitted. This embodiment also has the same effects as the first embodiment.

FIG. 15 is a perspective view showing a cross section of a semiconductor device 150 according to a third embodiment of the present invention. The semiconductor device 150 is configured by forming a plurality of layers of metal film wiring on the semiconductor substrate 158 and an insulating film between the respective layers, similarly to the semiconductor device 31 shown in the above-described first embodiment.

Assuming that semiconductor device 150 is formed of, for example, a P-channel MOS transistor,
The semiconductor substrate 158 is formed by diffusing an impurity such as boron into the n-type semiconductor substrate 151 to form a source diffusion layer 153 and a drain diffusion layer 154 so as to form a column perpendicular to the cross section.

After forming a diffusion layer to be an element of each MOS transistor, an oxide film 152 is formed on the surface of the semiconductor substrate 158. A contact is formed at a predetermined position in oxide film 152, and a source wiring 161 and a drain wiring 162 described later are directly connected to semiconductor substrate 158 by the contact. First layer source wiring 16
Numeral 1 is connected to two adjacent source diffusion layers 153 in common, and is formed to have a comb shape. A column-shaped drain wiring 162 is formed so as to be connected to the drain diffusion layer 154 between each column of the first-layer source wiring 161 and on one end 158a side of the semiconductor substrate 158.
The gate wiring 163 is formed in the semiconductor substrate 1 so as to form a column between the first-layer source wiring 161 and the drain wiring 162.
58 is formed via an oxide film 152.

In the semiconductor device 150, the second-layer source wiring 164 is formed so as to cover the wirings formed as described above, similarly to the second-layer emitter wiring 11 in the semiconductor device 31 described above.

Semiconductor device 150 configured as described above
In the above, when the ratio of the current value of each MOS transistor row is obtained using the above-described equation (2), it can be confirmed that the variation of the current value has been improved similarly to the semiconductor device 31 in the first embodiment. it can.

Therefore, the semiconductor device 1 of this embodiment
Also in 50, similarly to the semiconductor device 31 in the first embodiment, it is possible to reduce the difference in the value of the current flowing between each MOS transistor row formed in a row, and to widen the safe operation area. .

Also in this embodiment, the drain wiring 162 not covered by the second-layer source wiring 164 has
Since the layer drain wiring 165 is formed, the cross-sectional area can be increased on one end 158a side of the semiconductor substrate 158 without increasing the width of the wiring, and the size of the substrate can be reduced. .

[0083]

As described above, according to the present invention, the first emitter wiring of each transistor in the semiconductor device is commonly connected by the second emitter wiring formed so as to cover each transistor. Wiring to the transistor is eliminated, so that the resistance of the emitter wiring becomes sufficiently small.
The variation in the resistance of the emitter wiring is also reduced. Therefore, variation in the value of the current flowing through each transistor can be suppressed to be small, so that the safe operation area of the semiconductor device can be expanded, and the amount of current that can be handled can be increased.

Further, the first collector wiring covered by the second emitter wiring is formed so as to be wider than the first collector wiring not covered by the second emitter wiring. The cross-sectional area is widened, and the occurrence of disconnection of wiring due to electromigration can be suppressed.

Further, since the second collector wiring is formed on the first collector wiring which is not covered with the second emitter wiring, the cross-sectional area can be increased without increasing the wiring area. In addition, it is possible to suppress disconnection of wiring due to electromigration, and it is possible to reduce the size of a semiconductor substrate on which a semiconductor device is formed.

Further, according to the present invention, even when a unipolar transistor is formed in the semiconductor device, the same effect as that when the bipolar transistor is formed can be obtained.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a cross section of a semiconductor device 31 according to a first embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor device 31 according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view taken along line II of FIG. 2;

FIG. 4 is a cross-sectional view taken along the line II-II in FIG. 2;

FIG. 5 is a plan view of an n-type buried diffusion layer 2, an n-type epitaxial layer 3, and a p-type isolation diffusion layer 4 formed on a p-type semiconductor substrate 1.

6 is a plan view of an n-type collector compensation diffusion layer 5 and a p-type base diffusion layer 6 formed in the n-type epitaxial layer 3. FIG.

FIG. 7 is a plan view of an n-type emitter diffusion layer 7 formed in the n-type epitaxial layer 3.

8 is a plan view of an oxide film 8 formed on a semiconductor substrate 21. FIG.

9 is a plan view of a first-layer wiring 9 formed on a semiconductor substrate 21. FIG.

FIG. 10 is a plan view of a semiconductor substrate 21 on which an insulating film 10 is formed.

11 is a plan view of a second-layer emitter wiring 11 and a second-layer collector wiring 37 formed on the semiconductor substrate 21. FIG.

FIG. 12 is a plan view showing the first-layer emitter wiring 9a and the second-layer emitter wiring 11 in the semiconductor device 31 in an overlapping manner.

FIG. 13 is a graph showing a current ratio flowing through each transistor row.

FIG. 14 is a plan view of a semiconductor device 51 according to a second embodiment of the present invention.

FIG. 15 shows a semiconductor device 150 according to a third embodiment of the present invention.
FIG. 3 is a perspective view showing a cross section of FIG.

FIG. 16 is a perspective view showing a cross section of a semiconductor device 61 which is a conventional example.

17 is a plan view of the semiconductor device 61. FIG.

FIG. 18 is a cross-sectional view taken along line III-III in FIG. 17;

19 is a cross-sectional view taken along the line IV-IV in FIG.

20 is an equivalent circuit diagram of the semiconductor device 61. FIG.

FIG. 21 is a diagram in which wiring patterns of a first-layer emitter wiring portion 68 and a second-layer emitter wiring portion 81 in the semiconductor device 61 are superimposed.

FIG. 22 is a perspective view showing a cross section of a semiconductor device 100 as another conventional example.

[Explanation of symbols]

 Reference Signs List 1 p-type semiconductor substrate 2 n-type buried diffusion layer 3 n-type epitaxial layer 4 p-type separation / diffusion layer 5 n-type collector compensation diffusion layer 6 p-type base diffusion layer 7 n-type emitter diffusion layer 8 oxide film 9 first layer wiring 10 Insulating film 11 Second layer emitter wiring 12 Protective film 13 Emitter contact 14 Base contact 15 Collector contact 16 Balance resistor 17 Collector through hole 18 Emitter through hole 19 Emitter pad 20 Collector pad 21 Semiconductor substrate 31, 51 Semiconductor device

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 29/78 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 29/732 H01L 21/3205 H01L 21/331 H01L 21/8222 H01L 27/082 H01L 29/78

Claims (6)

(57) [Claims] A first emitter wiring on a semiconductor substrate;
A plurality of transistors formed by forming a base wiring and a first collector wiring are arranged adjacent to each other in a line, and the base wiring, the first collector wiring, and the first emitter wiring of each transistor are commonly used. , A first emitter wiring of each transistor is commonly connected by a second emitter wiring formed so as to cover each transistor, and a first collector covered by the second emitter wiring. The wiring is formed wider than the first collector wiring not covered by the second emitter wiring, and the first collector wiring not covered by the second emitter wiring has a second collector wiring. Are formed by laminating. 2. A semiconductor device comprising: a plurality of transistors formed by forming an emitter region, a base region, and a collector region adjacent to each other on a semiconductor substrate; In a semiconductor device in which a base region, a collector region, and an emitter region of a column are connected to a common base line, a first collector line, and a first emitter line, respectively, the first emitter line of each transistor column is A first collector wiring which is commonly connected by a second emitter wiring formed so as to cover the transistor row, and which is covered by the second emitter wiring, is a first collector wiring which is not covered by the second emitter wiring. The first collector wiring formed wider than the collector wiring and not covered by the second emitter wiring includes: A semiconductor device, wherein a second collector wiring is formed by lamination. 3. The semiconductor substrate according to claim 1, wherein an emitter pad and a collector pad for supplying a current to each of the transistor rows via the first emitter wiring and the first collector wiring are provided on the same side of the semiconductor substrate. Item 3. The semiconductor device according to item 2. 4. The semiconductor device according to claim 1, wherein the first emitter wiring and the first collector wiring are formed in a comb shape, and the first emitter wiring and the first collector wiring are meshed with each other. Item 4. The semiconductor device according to item 2 or 3. 5. The semiconductor device according to claim 1, wherein the second collector wiring is formed on the first collector wiring, which is not covered with the second emitter wiring, on a contact portion with the collector region. The semiconductor device according to claim 4. 6. A plurality of transistor rows each including a plurality of transistors formed by forming a source region, a gate region, and a drain region adjacent to each other on a semiconductor substrate are formed in a row. Column gate area,
In a semiconductor device in which a drain region and a source region are connected to a common gate wiring, a first drain wiring, and a first source wiring, respectively, a first source wiring of each transistor row covers the plurality of transistor rows. The first drain wiring, which is commonly connected by the second source wiring formed in the first wiring and is covered by the second source wiring, is wider than the first drain wiring not covered by the second source wiring. A first drain wiring not covered with the second source wiring, a second drain wiring is formed by lamination on a contact portion with the drain region. apparatus.