JPH1154708A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a bipolar transistor circuit device including a resistance element whose resistance is set with extremely high precision. SOLUTION: An anode region 18 is formed on the surface of a diode forming region 6 on a semiconductor substrate 3 at the same time as a base region 8 of a bipolar transistor under the same condition. A cathode region 19 is formed on the surface of the diode forming region 6 in the semiconductor substratum 3 while having a partial overlap region 20 with the anode region 18 and formed at the same time as an emitter region 9 of the bipolar transistor under the same condition. By using the cathode region 19 and the anode region 18, a Zener diode for zapping is constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having an NPN type bipolar transistor and having a zapping zener diode.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device having an NPN-type bipolar transistor, it is desired to incorporate a resistance element whose resistance value is set with extremely high precision which cannot be realized by a semiconductor wafer process. In order to obtain a resistance element whose resistance value is set with extremely high accuracy, a zener diode is formed when forming an NPN-type bipolar transistor, and this zener diode is connected to an adjustment resistance element constituting the resistance element. And
After a semiconductor wafer process, a method of adjusting a resistance value depending on whether or not a short circuit occurs between a cathode electrode and an anode electrode to obtain a resistance element whose resistance value is set with extremely high accuracy (generally, a zener zapping method) Is known).

A zapping zener diode used in the zener zapping method is known, for example, from Japanese Patent Application Laid-Open No. 6-13630. FIG. 13 shows a diode for zapping disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 6-13630, 101 is an N ⁺ diffusion layer which takes the potential of an island region, 102 is a contact window of the N ⁺ diffusion layer 101, 103
Is a P diffusion layer, 104 is an N ⁺ diffusion layer, 105 is an N ⁺ diffusion layer 1
Reference numeral 04 denotes a contact window, reference numeral 106 denotes a contact window of the P diffusion layer 103, and reference numeral 107 denotes an isolation region. The diode for zapping includes a P diffusion layer 103 and an N ⁺ diffusion layer 104.

[0004]

However, the zapping diode thus configured is a P-type diffusion layer.
Since forming by providing an N ⁺ diffusion layer 104 in the 3, N ⁺
When the diffusion layer 104 is formed, the implanted N-type impurity is neutralized to the P-type impurity of the P diffusion layer 103. as a result,
The impurity concentration of N ⁺ diffusion layer 104 decreases. In particular, when a zapping diode is formed without increasing the number of manufacturing steps of a semiconductor wafer process in a semiconductor integrated circuit device including an NPN-type bipolar transistor, the impurity concentration of the N ⁺ diffusion layer 104 is low, and Only a relatively high voltage was obtained. When the breakdown voltage is high as described above, a large amount of electric power is required to make a short circuit between the cathode electrode and the anode electrode.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in view of the above-mentioned problems, and provides an NPN-type bipolar transistor including a zapping diode having a low breakdown voltage without increasing the number of manufacturing steps of a semiconductor wafer process. It is an object to obtain a semiconductor integrated circuit device.

[0006]

A semiconductor integrated circuit device according to a first aspect of the present invention has a P-type semiconductor substrate and an N-type epitaxial growth layer formed on the surface of the semiconductor substrate, each of which is epitaxially grown. A semiconductor substrate having a transistor formation region and a diode formation region surrounded by a P-type device isolation region extending from the surface of the layer to the surface of the semiconductor substrate; and a base formed of a P-type diffusion region on the surface of the transistor formation region An NPN-type bipolar transistor having a region and an emitter region formed by an N-type diffusion region having an impurity concentration higher than that of the epitaxial growth layer on the surface of the base region; and a bipolar transistor on the surface of the diode formation region. Same impurity concentration and diffusion depth as P-type diffusion region forming base region Anode region formed in P-type diffusion region having, and the surface of the diode forming region,
An N-type diffusion region having the same impurity concentration and diffusion depth as the N-type diffusion region constituting the emitter region of the bipolar transistor is arranged along one main surface with a partially overlapping region with the anode region. A zapping diode having a cathode region, a zapping anode pad formed on a surface of the semiconductor substrate and electrically connected to an anode region of the diode, and a cathode region of the diode formed on a surface of the semiconductor substrate. And a zapping cathode pad that is electrically connected to the zapping cathode pad.

A semiconductor integrated circuit device according to a second aspect of the present invention
It has a P-type semiconductor substrate and an N-type epitaxial growth layer formed on the surface of the semiconductor substrate, each of which is surrounded by a P-type element isolation region reaching from the surface of the epitaxial growth layer to the surface of the semiconductor substrate. A semiconductor substrate having a transistor formation region and a diode formation region; a base region formed by a P-type diffusion region on the surface of the transistor formation region; and N having an impurity concentration higher than that of the epitaxial growth layer on the surface of the base region. NPN-type bipolar transistor having an emitter region formed by a P-type diffusion region, and a P-type transistor having the same impurity concentration and diffusion depth as the P-type diffusion region forming the base region of the bipolar transistor on the surface of the diode formation region. Region and diode formed in a diffusion region N-type diffusion region having the same impurity concentration and diffusion depth as the N-type diffusion region constituting the emitter region of the bipolar transistor, arranged along the surface with the anode region partially overlapping with the surface of the formation region. And a PN junction between the overlapping region and one of the anode region and the cathode region, and a high-concentration PN in a non-overlapping region between the anode region and the cathode region. A zapping diode having a junction, a zapping anode pad formed on the surface of the semiconductor substrate and electrically connected to an anode region of the diode, and a zapping anode pad formed on the surface of the semiconductor substrate and connected to a cathode region of the diode. And a zapping cathode pad which is electrically connected.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. 1 to 9 show a first embodiment of the present invention. 1 and 2, reference numeral 1 denotes a P-type semiconductor substrate having a resistance of, for example, 20 Ωcm. Since the semiconductor substrate 1 gives the substrate potential of the NPN-type bipolar transistor, the ground potential is given in the first embodiment. Reference numeral 2 denotes an N-type epitaxial growth layer formed on the surface of the semiconductor substrate, and forms a semiconductor base 3 with the semiconductor substrate 1. Reference numeral 4 denotes a P-type element isolation region extending from the surface of the epitaxial growth layer 2 to the surface of the semiconductor substrate 1 and, for example, boron (B) is ion-implanted at a high concentration.

Reference numeral 5 denotes a transistor forming region comprising the island region of the epitaxial growth layer 2 surrounded by the inter-element isolation region 4, and 6 denotes a diode comprising the island region of the epitaxial growth layer 2 surrounded by the inter-element isolation region 4. It is a formation area. Reference numeral 7 denotes a buried region formed with N-type impurities buried in the interface between the epitaxial growth layer 2 and the semiconductor substrate 1 in the transistor formation region 5. In the first embodiment, phosphorus is added to the surface of the semiconductor substrate 1. (P)
Is formed by ion implantation.

Reference numeral 8 denotes a base region formed by a P-type diffusion region on the surface of the transistor forming region 5. In the first embodiment, for example, 4 × 10 ¹⁴ / cm ² and 50 keV
Is formed by ion-implanting boron (B) under the following conditions. Reference numeral 9 denotes an emitter region formed on the surface of the base region by an N-type diffusion region having an impurity concentration higher than that of the epitaxial growth layer 2. In the first embodiment, for example, 4 × 10 ¹⁵ / cm ² 50 ke
It is formed by ion-implanting phosphorus (P) under the condition of V. Reference numeral 10 denotes a collector extraction region formed on the surface of the transistor formation region 5 separated from the base region 7 at the same time as the formation of the emitter region 8 under the same conditions. The NPN-type bipolar transistor is constituted by the island region of the epitaxial growth layer 2 in the transistor forming region 5 serving as the collector region, the base region 8 and the emitter region 9.

Reference numeral 11 denotes an insulating film (oxide film) formed on the surface of the semiconductor substrate 3, and 12 denotes the collector lead-out region 1.
0, the contact hole 13 formed in the insulating layer 11
, A collector wiring (electrode) electrically connected (ohmic contact) through the gate electrode and formed of an aluminum layer. Reference numeral 14 denotes a base wiring (electrode) electrically connected (ohmic contact) to the base region 8 via a contact hole 15 formed in the insulating layer 11, and is formed of an aluminum layer at the same time as the collector wiring 12. Is done. Reference numeral 16 denotes an emitter wiring (electrode) electrically connected (ohmic contact) to the emitter region 9 via a contact hole 17 formed in the insulating layer 11.
It is formed of an aluminum layer at the same time as the collector wiring 12.

Reference numeral 18 denotes the surface of the diode forming region 6 which has the same impurity concentration and the same diffusion depth as the P-type diffusion region constituting the base region 8 of the NPN bipolar transistor. in the anode region formed in P-type diffusion region formed of a high impurity concentration than the concentration, simultaneously with the base region 8 of the NPN bipolar transistor is formed under the same conditions, e.g., at 4 × 10 ¹⁴ / cm ² 50keV Is formed by ion-implanting boron (B) under the following conditions. This anode region 18 has a square shape as shown in FIG.

Reference numeral 19 denotes an NPN-type bipolar transistor which is formed along a first direction (a left-right direction in FIG. 2) with a region 20 partially overlapping the anode region 18 on the surface of the diode forming region 6. Emitter region 9 of transistor
A cathode region formed of an N-type diffusion region having the same impurity concentration and the same diffusion depth as the N-type diffusion region and having an impurity concentration higher than the impurity concentration of the epitaxial growth layer 2; It is formed simultaneously with the emitter region 9 of the bipolar transistor under the same conditions, for example, by ion-implanting phosphorus (P) at 4 × 10 ¹⁵ / cm ² at 50 keV.
The cathode region 19 and the anode region 18 constitute a zapping zener diode. The cathode region 19 has a square shape as shown in FIG. However, the width in a second direction (vertical direction in FIG. 2) orthogonal to the first direction is shorter than the width of the anode region 18.

[0014] Since the overlapping area 20 between the anode region 18 and the cathode region 19, which in the first embodiment, the impurity concentration of the anode region 18 are higher than the impurity concentration of the cathode region 19, N ^- Indicates the type. Therefore, the PN of the Zener diode constituted by the anode region 18 and the cathode region 19
The junction is a P ⁺ N ⁻ junction 2 between the N ⁻ type overlap region 20 and the P ⁺ type anode region 18 shown by a thick line in FIGS.
0a and P ^+, which is a junction between the side surface of the P + type anode region 18 and the bottom surface of the N ⁺ type cathode region 19 shown in FIG.
An N ⁺ junction 20b and P ⁺ located at both ends of the bold line shown in FIG.
P ⁺ N ⁺ junction 20c between the negative electrode region 18 and the N ⁺ type cathode region 19.

In short, the Zener diode composed of the anode region 18 and the cathode region 19 has a P ⁺ N ^- junction 20a between the overlap region 20 and the cathode region 19, and has a non-junction between the anode region 18 and the cathode region 19. The overlapping region, in other words, the boundary between the side surface on the cathode region 19 side along the second direction of the anode region 18 and the bottom surface of the cathode region 19, and the second region of the anode region 18
The high concentration P ⁺ N ⁺ junctions 20b and 20c will be provided at the boundary between the side surface on the cathode region 19 side in the direction of and the both side surfaces of the cathode region 19 in the first direction.

Reference numeral 22 denotes an anode wiring (electrode) electrically connected (ohmic contact) to the anode region 18 through a contact hole 21 formed in the insulating film 11, and a collector of the NPN bipolar transistor. It is formed of an aluminum layer at the same time as the wiring for use 12. The anode wiring 22 is electrically connected to a zapping anode pad PA formed in a peripheral portion on the surface of the semiconductor substrate 3, as shown in FIG.

Reference numeral 23 denotes a cathode wiring (electrode) electrically connected (ohmic contact) to the cathode region 19 through a contact hole 24 formed in the insulating film 11, and is made of the same aluminum as the anode wiring 21. It is formed by layers. This cathode wiring 23 is
It is electrically connected to a zapping cathode pad PK formed in a peripheral portion on the surface of the semiconductor substrate 3. Reference numeral 25 denotes an interlayer insulating film such as a BPSG film or / and silicon nitride (Si) which covers the NPN bipolar transistor and the Zener diode.
N) is an insulating layer made of a surface protective film such as N.

The size of the planar shape on the exposed surface of the Zener diode constituted by the anode region 18 and the cathode region 19 is determined in the first embodiment.
In, for example, the following is performed. The diode forming region 6 surrounded by the device isolation region 4 is a first region.
Is 23 μm in the direction along the direction, and 14 μm in the second direction. Each of the cathode region 19 and the anode region 18 is the first region shown in FIG.
The lengths a and b along the direction are 11 μm, and the lengths (widths) g1 and g2 along the second direction are each 10 μm.
m, 8 μm.

The planar shape of the contact hole 22 is a square having a length in the first direction of 2 μm and a length in the second direction of 7 μm. Contact hole 24
Is a square having a length along the first direction of 2 μm and a length along the second direction of 5 μm. The length (distance) c from the contact hole 22 to the cathode region 19 in the first direction and the length (distance) d from the contact hole 24 to the anode region 18 in the first direction are: Each is 4.5 μm.

The length e of the overlapping region 20 between the anode region 18 and the cathode region 19 along the first direction is 3 μm. Length (distance) f of the contact hole 24 and the contact hole 22 along the first direction
Is 12 μm. Note that the center lines of the anode region 18 and the cathode region 19 along the first direction coincide with the center lines of the diode formation region 6 along the first direction. In addition, the distance between the outer side of the anode region 18 along the second direction and the side of the element isolation region 4 facing the side is equal to the outer side of the cathode region 19 along the second direction. The distance to the side of the inter-element isolation region 4 opposed to this side is set to match.

When the characteristics of the Zener diode thus formed were measured, the characteristics as shown in FIG. 3 were obtained. As is clear from FIG. 3, the forward voltage is 0.7 V, and the breakdown voltage (reverse breakdown voltage, breakdown voltage) shows a very low value of 3.5 V.
Very suitable characteristics were obtained as a zapping diode that can easily short-circuit the cathode electrode and the anode electrode.

For example, a cathode pad PK for zapping
When a current of about 50 mA was applied to the zapping anode pad PA, the Zener diode was easily short-circuited between the cathode wiring 23 and the anode wiring 21. That is, from the cathode wiring 23 to the anode wiring 21
Of the cathode wiring 23 is melted, and aluminum-silicon (Al) is formed on the surface layer from the cathode region 19 where the cathode wiring 23 is in contact to the anode region where the anode wiring 21 is in contact. An AlSi) layer is formed, and the cathode wiring 23 and the anode wiring 21 are short-circuited.

At this time, the resistance value is determined by connecting a gold wire to each of the zapping cathode pad PK and the zapping anode pad PA, flowing a current, and measuring the voltage between the zapping cathode pad PK and the zapping anode pad PA. As a result of measurement, the value was as low as 10Ω. This 10Ω is the resistance value of the gold wire, the contact resistance between the gold wire and the zapping cathode pad PK and the zapping anode pad PA, the respective resistances of the cathode wiring 23 and the anode wiring 21, and the resistance between the cathode wiring 23 and the cathode region 19. Since the contact resistance and the contact resistance between the anode wiring 21 and the anode region 18 are also included, the resistance value between the cathode wiring 23 and the anode wiring 21 is a low value of about several Ω, and It can be said that a short circuit state is substantially formed between the wiring 21 and the wiring 21. Therefore, the Zener diode thus configured is very suitable as a zapping diode.

Next, in the semiconductor integrated circuit device configured as described above, a method of obtaining a resistance element whose resistance value is set with extremely high accuracy by using a zapping diode will be described with reference to FIGS. It will be described using FIG. FIG.
5 and FIG. 5, A is one end node of the resistance element which requires an extremely high-precision resistance value, B is the other end node of the resistance element, and an extremely high-precision resistance value between the one end node and the one-side node. Required.

PK1 is a semiconductor substrate 3 on which an NPN-type bipolar transistor and a Zener diode are formed.
A first zapping cathode pad formed in a peripheral portion on the surface of the semiconductor substrate, PK2 is a second zapping cathode pad formed in a peripheral portion on the surface of the semiconductor substrate 3, and PK3 is a surface of the semiconductor substrate 3 A third zapping cathode pad formed on the upper peripheral portion, PA is a zapping anode pad formed on the peripheral portion of the surface of the semiconductor substrate 3.

Reference numeral 26 denotes a resistor main body having one end connected to the one end side node A and having a resistance value R0.
, That is, a diffusion resistance formed by a diffusion region formed in an island region of the epitaxial growth layer surrounded by the element isolation region 4. Reference numeral 27 denotes a first resistor having a resistance value R1 whose one end is connected to the other end of the resistor main body 26.
Is a diffusion resistance formed by a diffusion region formed on the surface of the semiconductor substrate 3, that is, an island region of the epitaxial growth layer surrounded by the inter-element isolation region 4. In this example, the resistance is a resistance. The value R1 is set to, for example, 1/100 of the resistance value R0 of the resistor main body 26.

Reference numeral 28 denotes a second adjustment resistor having one end connected to the other end of the first adjustment resistor 27 and having a resistance value R2. The second adjustment resistor 28 has a surface, that is, the inter-element isolation region 4 Is a diffusion resistance formed by a diffusion region formed in the island region of the epitaxial growth layer surrounded by the above. In this example, the resistance value R2 is set to, for example, 1/100 of the resistance value R0 of the resistance main body 26. Reference numeral 29 denotes a third adjustment resistor having one end connected to the other end of the second adjustment resistor 28 and the other end connected to the other end side node B and having a resistance value R3. The diffusion resistance is a diffusion resistance formed on the surface, that is, a diffusion region formed in the island region of the epitaxial growth layer surrounded by the element isolation region 4. In this example, the resistance value R3 is, for example, the resistance value of the resistance main body 26. It is 1/100 of R0. The resistor body 26 and the first to third adjusting resistors 27 to 2
9 is connected in series between the one end side node A and the other end side node B to form a resistance element.

Numeral 30 indicates that the cathode region 19 is connected to the other end of the resistor body 26 and the first zapping cathode pad PK1 via the cathode wiring 23, and the anode region 18 is connected to the anode wiring 21 via the anode wiring 21. A first zapping diode ZD1 connected to the other end node B and the zapping anode pad PA
Thus, it is formed on the surface of the semiconductor substrate 3 and has the configuration of the Zener diode shown in FIG. Numeral 31 indicates that the cathode region 19 is connected to the other end of the first adjusting resistor 27 and the second zapping cathode pad PK2 via the cathode wiring 23, and the anode region 18 is connected to the anode wiring 21 via the anode wiring 21. A second zapping diode ZD2 connected to the other end side node B and the zapping anode pad PA is formed on the surface of the semiconductor substrate 3 and has the configuration of the zener diode shown in FIG. 32 is a cathode region 19 in which the cathode wiring 2
3 is connected to the other end of the second adjusting resistor 28 and the third zapping cathode pad PK3, and the anode region 18 is connected to the other end node B and the zapping via an anode wiring 21. The third zapping diode ZD3 connected to the anode pad PA for use is formed on the surface of the semiconductor substrate 3 and has the configuration of the Zener diode (ZD) shown in FIG.

Next, the setting of the resistance value in the resistance element having such a configuration will be described. After the completion of the wafer process, first, a resistance value R00 between one end node A and the other end node B is measured. The resistance value R00 at this time is given by the following equation (1). R00 = R0 + R1 + R2 + R3 (1) If the resistance value R00 has reached a desired value, the setting ends.

If the desired value is not attained, a current is passed from the third zapping cathode pad PK3 to the zapping anode pad PA, and a current is applied between the cathode wiring 23 and the anode wiring 21 for the third zapping diode 32. Is in a short-circuit state, and as shown in FIG. 6, the both ends of the third adjusting resistor 29 are substantially in a short-circuit state. After the both ends of the third adjusting resistor 29 are substantially short-circuited, the resistance value R between one end node A and the other end node B is set.
Measure 10. The resistance value R10 at this time is represented by the following equation (2). R10 = R0 + R1 + R2 <R00 (2) If the resistance value R10 has reached a desired value, the setting ends.

If the desired value is not attained, a current is further passed from the second zapping cathode pad PK2 to the zapping anode pad PA, and the cathode wiring 23 and the anode wiring 21 for the second zapping diode 31 are connected. Are short-circuited, and as shown in FIG. 7, both ends of the series resistors of the second and third adjusting resistors 28 and 29 are substantially short-circuited. After the two ends of the series resistance of the second and third adjustment resistors 28 and 29 are substantially short-circuited, the resistance value R20 between the one end node A and the other end node B is measured. The resistance value R20 at this time is expressed by the following equation (3). R20 = R0 + R1 <R10 <R00 (3) If the resistance value R10 has reached a desired value, the setting ends.

Although FIG. 7 does not show the third zapping diode 32 in a substantially short-circuit state, after the third zapping diode 32 is substantially short-circuited as described above, Zapping diode 3
1 may be in a substantially short-circuit state. Also, the resistance value R0
Depending on the value of 0, the second zapping diode 31 may be substantially directly short-circuited. In either case, the resistance R20 will be substantially the same.

If the resistance value R10 is not the desired value, the first zapping cathode pad P
A current is passed from K1 to the zapping anode pad PA to short-circuit the cathode wiring 23 and the anode wiring 21 for the first zapping diode 30,
As shown in FIG. 8, the first to third adjusting resistors 27 to
The two ends of the series resistor 29 are substantially short-circuited. After the both ends of the series resistors of the first to third adjusting resistors 27 to 29 are substantially short-circuited, the resistance value R20 between the one end node A and the other end node B is measured. The resistance value R30 at this time is expressed by the following equation (4). R30 = R0 <R00 <R10 <R00 (4) The setting of the resistance value is thus completed, and a resistance element having a resistance value very close to a desired value (design value) is obtained.

Although FIG. 8 does not show the second and third zapping diodes 31 and 32 in a substantially short-circuited state, as described above, the second and third zapping diodes 31 and 32 are substantially short-circuited. After the first short-circuiting state, the first zapping diode 33 may be substantially short-circuited. Further, depending on the value of the resistance value R00, the first zapping diode 30 may be substantially directly short-circuited. In either case, the resistance R30 will be substantially the same.

In the semiconductor integrated circuit device having the above-described configuration, a device provided with an NPN-type bipolar transistor can be used for zapping simultaneously with the manufacture of the NPN-type bipolar transistor without any additional manufacturing process. This has the effect that a diode can be manufactured and a resistance element whose resistance value is set with extremely high precision can be built in.

In the first embodiment, the zapping diode used for adjusting the resistance value of the resistance element is shown. However, the zapping diode is used not only for adjusting the resistance value but also as shown in FIG. As shown in (1), the bipolar transistor 41 may be used as a zapping diode for use or non-use.

In FIG. 9, reference numeral 42 denotes a resistor connected between the base and the emitter of the NPN bipolar transistor 41, and reference numeral 43 denotes a resistor connected between the base of the transistor 41 and the zapping cathode pad PK. . When using the bipolar transistor 41, the zapping diode 44 is left as it is. Since the reverse withstand voltage of the zapping diode 44 is large,
It does not affect the bipolar transistor 41 at all.
Therefore, bipolar transistor 41 operates according to a signal input to base node 46, and collector node 4
5 outputs a signal corresponding to the signal input to the base node 46.

When the bipolar transistor 41 is not used, a current flows from the zapping cathode pad PK to the zapping anode pad PA to short-circuit the cathode wiring 23 and the anode wiring 21 for the zapping diode 44, The base-emitter of the bipolar transistor 41 is substantially short-circuited. As a result, bipolar transistor 41 does not operate at all, and collector node 45 maintains an electrically floating state, that is, a high impedance state.

In the first embodiment described above, a device having a bipolar transistor has been described. However, a semiconductor integrated circuit device incorporating a P-type MOS transistor and an N-type MOS transistor, that is, a so-called BiCMO
The present invention may be applied to a semiconductor integrated circuit device commonly called S.

Further, in the first embodiment, the width of the cathode region 19 in the first direction is smaller than the width of the anode region 18 in the first direction. May be shorter than the width of the cathode region 19 in the first direction.

The widths of the anode region 18 and the cathode region 19 in the first direction are the same, and one of the anode region 18 and the cathode region 19 has, for example, a triangular planar shape on the other region side. The tapered portion may have a trapezoidal or arc-shaped tapered portion, and the tapered portion may form the partially overlapping region 20.

Embodiment 2 FIG. 10 shows a second embodiment of the present invention. The second embodiment is different from the first embodiment in that the shape of the cathode region 19, in other words, the anode region 18 and the cathode region 1 are different.
9 except for a partially overlapping area 20, and the other points are the same as in the first embodiment.
Therefore, this difference will be described in detail below. In FIG. 10, the same reference numerals as those in the drawings showing the first embodiment denote the same or corresponding parts.

That is, the second embodiment differs from the first embodiment in that the anode region 18
And the planar shape of the cathode region 19 is the same square,
The anode region 18 and the cathode region 19 are in the width direction (second
), And the overlapping region 20 is
In the direction of. In other words, the exposed side (exposed P ⁺ N ⁻ junction side) located above the anode region 18 and the epitaxial growth layer 2 in the diode formation region 6, and the upper side of the cathode region 19 and the epitaxial growth layer 2 in the diode formation region 6. At a distance h2 from the exposed side (exposed N ⁺ N ⁻ junction side). An exposed side (exposed P ⁺ N ⁻ junction side) located below the anode region 18 and the epitaxial growth layer 2 in the diode formation region 6, the cathode region 19, and the epitaxial growth layer 2 in the diode formation region 6.
And a distance h1 between the exposed side (exposed N ⁺ N ⁻ junction side) located on the lower side in the figure.

[0044] In thus constituted zener diode, PN junction constituted Zener diode by an anode region 18 and cathode region 19, N indicated by shown bold line ^- type overlapping region 20 and the P ⁺ -type A P ⁺ N ^- junction 20 a with the anode region 18, a P ⁺ N ⁺ junction 20 b (not shown) which is a junction between the side surface of the P ⁺ type anode region 18 and the bottom surface of the N ⁺ type cathode region 19, a P ⁺ N ⁺ junction 20c between the P ⁺ -type anode region 18 and the N ⁺ -type cathode region 19 located on both ends of the illustrated bold lines. In short, the Zener diode composed of the anode region 18 and the cathode region 19 has a P ⁺ N ⁻ junction 20a between the overlap region 20 and the anode region 18, and a non-overlap region between the anode region 18 and the cathode region 19, In other words, high-concentration P ⁺ N ⁺ junctions 20b and 20c are provided at the boundary between cathode region 19 and anode region 18.

In the second embodiment, the size of the planar shape on the exposed surface of the Zener diode constituted by the anode region 18 and the cathode region 19 is as follows, for example. Anode region 18
Each of the cathode regions 19 has a length a and b along the first direction of 11 μm, and lengths (widths) g1 and g2 along the second direction of 8 μm. Distances h1 and h2
Is 2 μm each. Length (distance) from contact hole 22 to cathode region 19 along the first direction
c and the length (distance) d from the contact hole 24 to the anode region 18 along the first direction are 4.
5 μm. The length e along the first direction of the overlapping region 20 between the anode region 18 and the cathode region 19 is 3 μm.
It is. Contact hole 24 and contact hole 22
Is along the first direction (distance) f is 12 μm. Each of the contact holes 24 and 22 has a length of 2 μm along the first direction and a length (width) along the second direction of 5 μm.

In the Zener diode thus configured, the same characteristics as those shown in FIG. 3 were obtained as in the first embodiment. In addition, the resistance when the current flows from the zapping cathode pad PK to the zapping anode pad PA and the cathode wiring and the anode wiring for the Zener diode are short-circuited as in the first embodiment is also described above. Values similar to those of the first embodiment are shown. Therefore, also in the second embodiment, the same effects as those in the first embodiment can be obtained.

Embodiment 3 FIG. 11 shows the third embodiment.
Is shown. In the third embodiment, the Zener diode is constituted by the anode region 18 and the cathode region 19 in the first embodiment described above, whereas the cathode region 19 and the first direction are formed. Anode regions 1 arranged on both sides of a cathode region 19 along
8 and 36, except that they constitute a Zener diode, and the other points are the same as in the first embodiment.

That is, the third embodiment differs from the first embodiment in that an anode region 36 having exactly the same structure as the anode region 18 is provided on the left side of the cathode region 19 in the drawing. It is provided. The anode region 36 is electrically connected (ohmic contact) to the anode wiring 21 via the contact hole 38. In FIG. 11, the same reference numerals as those given in the drawings showing Embodiment 1 denote the same or corresponding parts.

In the third embodiment, the size of the planar shape on the exposed surface of the Zener diode constituted by the anode regions 18 and 36 and the cathode region 19 is, for example, as follows. Anode region 1
Each of 8, 8 has a length a along the first direction shown in FIG. 11 of 10 μm and a length (width) along the second direction.
g1 is 10 μm. The cathode region 19 has a length b along the first direction of 11 μm and a length (width) g2 along the second direction of 8 μm.

The length (distance) c from the contact holes 22 and 38 to the cathode region 19 in the first direction and the length (distance) from the contact hole 24 to the anode regions 18 and 36 in the first direction (distance) ) D is 3μ each
m. Anode regions 18, 36 and cathode region 19
E along the first direction of the overlap regions 20, 37 with
Is 0.5 μm each. Contact hole 24,
The length (distance) f along the first direction between the contact hole 45 and the contact hole 22 is 7.5 μm. The planar shape of the contact holes 22 and 38 is a square having a length of 2 μm along the first direction and a length of 7 μm along the second direction. The planar shape of the contact hole 24 is 2 μm in length in the first direction and 5 μm in length in the second direction.
Is a rectangle.

The Zener diode thus formed has a partially overlapping region 20 between the anode region 18 and the cathode region 19 along the first direction, and the anode region 36 and the cathode region 19 First in between
Partially overlapped region 37 along the direction of. In the third embodiment, each of the overlapping regions 20 and 37 has the impurity concentration of the cathode region 19 in the anode region 1.
Since it is higher than the impurity concentrations of Nos. 8 and 36, it indicates N-type. Therefore, the PN junction of the Zener diode constituted by the anode regions 18 and 36 and the cathode region 19 is equivalent to the N ⁻ -type overlapping region 20 indicated by a thick line in FIG.
Between 37 and the P ⁺ -type anode region 18, 36 P ⁺ N ^- junction 20a, and 37a, a junction between the cathode region 19 bottom side and an N ⁺ -type P ⁺ -type anode region 18, 36 P ⁺ N ⁺ junctions 20b, 20b (not shown), and P ⁺ -type anode regions 18, 36 located at both ends of the bold line in the figure and N ⁺
P ⁺ N ⁺ junctions 20c and 37c with the cathode region 19 of the mold.

When the characteristics of the Zener diode were measured, the same characteristics as those shown in FIG. 3 were obtained as in the first embodiment. In addition, the zapping cathode pad PK to the zapping anode pad PA
As a result, a short circuit was established between the cathode wiring 23 and the anode wiring 21 for the Zener diode as in the first embodiment. The resistance value at this time was measured in the same manner as in the above-described first embodiment.
The value was as low as 5Ω. That is, the resistance value between the cathode wiring 23 and the anode wiring 21 is a low value of about several Ω, and it can be said that the cathode wiring 23 and the anode wiring 21 are substantially in a short-circuit state.

The Zener diode thus configured has the same effects as those of the first embodiment, and the cathode region 19 has the anode region 1 on both sides thereof.
Since the overlapping regions 20 and 37 are formed with the regions 8 and 36, respectively, the following effects are obtained. That is, in order to reduce the resistance value between the cathode wiring 23 and the anode wiring 21, the length (distance) f of the contact holes 22, 38 and the contact hole 24 along the first direction is reduced.
, Ie, the length e of the overlapping regions 20 and 37 can be designed to be small. At this time, for example, in the manufacturing process,
Even if a mask shift occurs in the mask for forming the cathode region 19 and the anode regions 18 and 36, no Zener diode is formed because at least one of the overlap regions 20 and 37 definitely forms the overlap region. Never. As a result, there is an effect that the Zener diode between the cathode wiring 23 and the anode wiring 21 is easily broken, and the resistance value between the cathode wiring 23 and the anode wiring 21 can be made extremely small.

In the third embodiment, similarly to the first embodiment, the anode regions 18, 3
6 in the first direction may be shorter than the width of the cathode region 19 in the first direction. Further, the widths of the anode regions 18 and 36 and the cathode region 19 in the first direction are the same, and one of the anode regions 18 and 36 and the cathode region 19 has a triangular planar shape on the other region side. , Trapezoidal, or arc-shaped tapered portions, and the tapered portions may form the partially overlapping regions 20 and 37. Further, the third embodiment described above
In, showed that disposed P ⁺ -type anode region 18, 36 on both sides of the N ⁺ type cathode region 19, placing the N ⁺ -type cathode region 19 on either side of the P ⁺ -type anode region 18 The same effect can be obtained even if the device is used.

Embodiment 4 FIG. 12 shows a fourth embodiment of the present invention. In the fourth embodiment, a plurality of components (in the fourth embodiment,
4 and 5 described in the first embodiment.
3) Zener diodes (ZD1 to ZD1)
The anode region 18 of 3) is configured to be common, and the other points are the same as those of the first embodiment. That is, the one shown in the fourth embodiment has an anode region 18 common to a plurality of Zener diodes,
Cathode regions 19A to 19C respectively corresponding to the plurality of Zener diodes are formed in the diode formation region 6 in the epitaxial growth layer 2 surrounded by the element isolation region 4.

The cathode regions 19A to 19C are arranged in parallel (parallel) along the second direction (the horizontal direction in FIG. 12). Each of the cathode regions 19A to 19C is an anode region 1
8 and a first direction (the vertical direction in FIG. 11) so as to partially overlap regions 20A to 20C. In the fourth embodiment, each of the overlapping regions 20A to 20C has an N- type because the impurity concentration of the cathode regions 19A to 19C is higher than that of the anode region 18 in the fourth embodiment. Thus, each of the PN junction of a plurality of zener diodes, N indicated by a thick line in FIG. 12 ^- -type overlap area 20A~20C and the P ⁺ -type P ⁺ N of the anode region 18 of the
^The junctions 20Aa to 20Ca and the P ⁺ type anode region 18
Side and an N ⁺ -type and a junction between the bottom surface of the cathode region 19A-19C P ⁺ N ⁺ junction 20Ab～20Cb (not shown), located on both ends of the illustrated bold line P ⁺ -type anode region 18 P ⁺ between N ⁺ -type cathode regions 19A to 19C
N ⁺ junctions 20Ac to 20Cc are obtained. In FIG. 13, the same reference numerals as those in the drawings showing the first embodiment denote the same or corresponding parts.

In each of the plurality of Zener diodes configured as above, the cathode regions 19A to 19
Since the relationship between C and the anode region 18 is the same as that of the first embodiment, the same characteristics as those shown in FIG. 3 were obtained. Therefore, even with such a configuration, in addition to the same effects as those of the first embodiment,
As shown in FIGS. 4 and 5, a common anode region 18 is used for a plurality of zapping diodes, so that the area occupied by the zapping diodes can be further reduced. The cathode region 1
The planar shape on the anode 18 side in 9A to 19C may be triangular, trapezoidal, or arcuate.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part showing a first embodiment of the present invention.

FIG. 2 is a plan view of a main part showing the first embodiment of the present invention.

FIG. 3 is a characteristic diagram showing characteristics of the Zener diode according to the first embodiment of the present invention.

FIG. 4 is a conceptual plan view showing a resistance element and a zapping diode according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing an initial state of the resistance element and the zapping diode according to the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing a first state of the resistance element and the zapping diode according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram showing a second state of the resistance element and the zapping diode according to the first embodiment of the present invention.

FIG. 8 is a circuit diagram showing a second state of the resistance element and the zapping diode according to the first embodiment of the present invention.

FIG. 9 is a circuit diagram showing an example in which the zapping diode according to the first embodiment of the present invention is applied to a transistor.

FIG. 10 is an essential part plan view showing Embodiment 2 of the present invention;

FIG. 11 is a main part plan view showing Embodiment 3 of the present invention.

FIG. 12 is an essential part plan view showing Embodiment 4 of the present invention.

FIG. 13 is a sectional view of a main part showing a conventional zapping diode.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate, 2 epitaxial growth layer, 3 semiconductor substrate, 4 element isolation region, 5 transistor formation region, 6 diode formation region, 8 base region, 9 emitter region, 18 anode region, 19 cathode region, 20 partially overlapping region.

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/866

Claims (7)

[Claims] 1. A semiconductor device comprising: a P-type semiconductor substrate; and an N-type epitaxial growth layer formed on a surface of the semiconductor substrate. Each of the P-type semiconductor layers reaches the surface of the semiconductor substrate from the surface of the epitaxial growth layer. A semiconductor substrate having a transistor formation region and a diode formation region surrounded by an element isolation region; a base region formed by a P-type diffusion region on the surface of the transistor formation region; An NPN-type bipolar transistor having an emitter region formed by an N-type diffusion region having an impurity concentration higher than the impurity concentration; a P-type diffusion region constituting a base region of the bipolar transistor on a surface of the diode formation region; A formed by a P-type diffusion region having the same impurity concentration and diffusion depth. The same region as the N-type diffusion region, which is disposed along one main surface on the surface of the diode formation region and partially overlaps with the anode region and forms the emitter region of the bipolar transistor. A zapping diode having a cathode region formed of an N-type diffusion region having a concentration and a diffusion depth; and a zapping diode formed on a surface of the semiconductor substrate and electrically connected to an anode region of the diode. A semiconductor integrated circuit device comprising: an anode pad; a zapping cathode pad formed on a surface of the semiconductor substrate and electrically connected to a cathode region of the diode. 2. An overlap between the anode region and the cathode region of the diode, wherein the width of one of the anode region and the cathode region overlaps at a position shorter than the width of the other region. The semiconductor integrated circuit device according to claim 1. 3. An anode region and a cathode region of the diode both have a square planar shape, one of the anode region and the cathode region has a smaller width than the other, and the partially overlapping region has a width. 2. The semiconductor integrated circuit device according to claim 1, wherein the region is a region overlapping in a direction orthogonal to the direction. 4. An anode region and a cathode region of the diode both have a square planar shape, and the anode region and the cathode region are displaced along the width direction, and the partially overlapping region is orthogonal to the width direction. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a region overlapping in a direction in which the semiconductor integrated circuit device moves. 5. One of the anode region and the cathode region of the diode is arranged along one main surface of the semiconductor substrate and sandwiches the other of the anode region and the cathode region of the diode. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device comprises a pair of regions. 6. The diode has a plurality of diode portions, and the cathode region has a plurality of cathode regions corresponding to the plurality of diode portions, each of which has one anode region common to the plurality of diode portions. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has an overlapping area and is arranged along one main surface. 7. A semiconductor device comprising: a P-type semiconductor substrate; and an N-type epitaxial growth layer formed on a surface of the semiconductor substrate. Each of the P-type semiconductor layers reaches the surface of the semiconductor substrate from the surface of the epitaxial growth layer. A semiconductor substrate having a transistor formation region and a diode formation region surrounded by an element isolation region; a base region formed by a P-type diffusion region on the surface of the transistor formation region; An NPN-type bipolar transistor having an emitter region formed by an N-type diffusion region having an impurity concentration higher than the impurity concentration; a P-type diffusion region constituting a base region of the bipolar transistor on a surface of the diode formation region; A formed by a P-type diffusion region having the same impurity concentration and diffusion depth. The same region as the N-type diffusion region, which is disposed along one main surface on the surface of the diode formation region and partially overlaps with the anode region and forms the emitter region of the bipolar transistor. A cathode region formed of an N-type diffusion region having a concentration and a diffusion depth, and having a PN junction between the overlap region and one of the anode region and the cathode region; A zapping diode having a high-concentration PN junction in a non-overlapping region between the anode region and the cathode region; a zapping anode formed on a surface of the semiconductor substrate and electrically connected to an anode region of the diode. A pad formed on a surface of the semiconductor substrate and electrically connected to a cathode region of the diode; A semiconductor integrated circuit device provided with a cathode pad for tapping.