JPH03204973A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a structure which hardly varies in contact resistance by a method wherein a heat treatment process, where silicon contained in a substrate is made to diffuse into the fine wire section of a first metal wire layer through a contact window and a dummy contact window and the fine wire section is substantially saturated with silicon, is prepared. CONSTITUTION:A dummy contact window DRC is provided to a semiconductor layer between a contact window RC and the extensions MET2 and MET2' of a metal wiring layer close to the contact window RC, as the reaction between Si of the substrate surface and Al of a wiring layer occurs at not only the contact window RC but also the dummy contact window DRC, a prescribed heat treatment is executed in a manufacturing process so as to enable Si to diffuse from the contact window RC into Al to such an extent that Al is saturated with Si. A metal wiring layer DMET fine in width is formed between the metal wiring layer on the dummy contact window DRC and the metal wiring layer on the contact window RC, so that Si hardly diffuses from the contact window RC. Moreover, a grounding wiring layer MET2 is connected to the contact window RC through the intermediary of the wiring layer MET2' fine in width. In result, a structure which hardly varies in contact resistance can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a novel structure that can maintain a constant contact resistance value between a resistance diffusion layer and a metal wiring layer formed on the surface of a semiconductor substrate of a semiconductor integrated circuit.

When designing a semiconductor integrated circuit, it is often necessary to strictly form the resistors in the circuit with a constant resistance ratio. An example of this is the current mirror circuit shown in FIG. L2. L, is a predetermined load circuit, and a current I2j,
is supplied. Vcc indicates a power supply, and GND indicates grounding. If the transistors TT 2 and T s are designed so that the withstand voltage V Be between the pace emitters, the current amplification factor hpi, etc. are the same, the current value I3. I2. The relationship of I2 is determined by the resistances R, , R, , R2. That is, I,,L,
1. is R,,R,,R.

Depends on. Therefore 12.1. In order to have a predetermined ratio, the ratio of R2 and R2 must be set to an appropriate value, and this ratio must be maintained at all times.

T1 in FIG. FIG. 2 shows a conventional plan view when the TLT2, R+, R2, and R4 portions are actually formed on a semiconductor substrate. In FIG. 2, the transistor T.

T, ,T, and resistances R, ,R, ,R,l are all designed to be the same.

Transistors T,, T2. T and C are formed in an island surrounded by an 8° isolation region, and C is an N-type collector region and is electrically connected to the metal wiring layer MC through the collector contact window CCW. B is a P-type base region, which is commonly connected to a metal wiring layer MB via a base contact window BCW. E is an N-type emitter region provided in the base region B, and is connected to the metal wiring layer ME from the emitter contact window ECW.
Connected to T1. Resistors R+, R2, Rs are also in the isolation region 1 s.

It is formed in the N-type region RES, which is an island surrounded by the P-type resistance diffusion layer RED. The resistance diffusion layer RED is connected to the resistance contact window RC at one end via the metal wiring layer METI to the transistors T, , T2 . T.

The other end is connected to the emitter of the metal wiring layer MET2 for grounding.

In such a circuit, the current 11. In order to make Ix and Is equal, it is necessary to form R+, R2, and Rz equally as described above. Therefore, a designer usually designs the size of the resistance diffusion layer RED, the size of the resistance contact window RC, etc. to be all equal. However, the actual resistance value is determined by the series resistance value of the resistance in the resistance diffusion layer RED and the contact resistance in the contact portion. The resistance value of the resistance diffusion layer RED is usually stable and hardly changes once it is formed, but the contact resistance changes due to heat treatment in the manufacturing process or changes over time during use.
The reaction between A1 and the metal wiring layer progresses, and Si diffuses into A1, resulting in changes. Therefore, no matter how accurately the pattern is designed, there is a problem in that R3 cannot be maintained at a predetermined ratio.

This point will be explained in more detail with reference to FIGS. 3 and 4.

FIG. 3 is a partial plan view of FIG. 2, showing a portion of the resistor R2.

FIG. 4 is a sectional view taken along line xx' in FIG. 3. 1
is a P-type Si semiconductor substrate, and 2 is an N-type semiconductor layer on its surface. A resistance diffusion layer RED made of a P-type impurity diffusion layer is formed on the surface thereof, and a contact window RC formed in the insulating film 3 connects the metal wiring layer MET1. MET
Connected to 2.

The resistances that substantially affect the circuit operation are the diffusion resistance DR of the diffusion layer RED and the contact resistance of the contact portion. The contact resistance changes due to the reaction between AI and Si,
In particular, when a large amount of AI exists, such as in the grounding wiring layer MET2, the diffusion of Si into the AI progresses even more actively, and its change becomes an important problem. By the way, the contact resistance of the contact part is the edge part 4 of the contact window where the current is concentrated.
It depends on how the reaction progresses. This is the diffusion layer RE
Since the resistance of D is very large compared to the resistance of the metal wiring layer MET2, it may be due to current concentration or the diffusion layer RED of the contact window RC.
This is because it occurs at the edge 4 on the extension side.

Therefore, in view of the above-mentioned conventional drawbacks, the present invention aims to provide a novel structure in which the contact resistance does not change. a step of forming a layer, a step of forming an insulating layer on the diffusion layer, a step of forming a contact window exposing a part of the diffusion layer on the insulating layer, and a dummy contact window adjacent to the contact window. A first metal wiring layer connecting the contact window and the dummy contact window, and having a thin line portion between the contact window and the dummy contact window that is narrower than the width of both windows, is connected to the insulating layer. forming a second metal wiring layer connected to the first metal wiring layer at a position opposite to the contact window with the dummy contact window in between;
manufacturing a semiconductor device, comprising a heat treatment step for substantially saturating silicon of the substrate by diffusing silicon in the thin wire portion of the first metal wiring layer through the contact window and the dummy contact window; method.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 5 is a partial plan view when this embodiment is applied to FIG. 3, and FIG. 6 is a sectional view taken along YY' in FIG. Fifth
, 6 are given the same reference numerals as those in FIGS. 3 and 4.

The first point of this embodiment is the extension of the contact window RC and the metal wiring layer in the vicinity of the contact window RC.

ET2. Dummy contact window D between MET2'
This is due to the establishment of RC. By doing so, the reaction between Si on the substrate surface and A1 in the wiring layer occurs not only in the contact window RC but also in the dummy contact window DRC. Normally, the diffusion of Si into Al reaches saturation when the amount of Si in A1 reaches about 1% and does not proceed any further.

Therefore, the amount of AI required for diffusion of Si from the dummy contact window RC becomes small, and saturates quickly. Therefore, if a predetermined heat treatment is performed in the manufacturing process to saturate the diffusion of Si from the contact window RC into Al, the diffusion at the edge portion 4, which has a substantial effect on the contact resistance, will proceed further. First, the contact resistance does not change.

Furthermore, the second point of this embodiment is that the metal wiring layer DMET between the metal wiring layer above the contact window RC and the metal wiring layer above the dummy contact window DRC is formed to have a narrow width. In other words, the diffusion of Si from the contact window RC becomes saturated due to the diffusion of St from the dummy contact window DRC, without being able to diffuse toward the metal wiring layer MET2 side. However, by making the metal wiring layer DMET narrower, The diffusion of Si from the contact RC becomes even more difficult.

The third point in this embodiment is that in the conventional example shown in FIG. It is connected via MET2'. By doing this, a large amount of A1 in the grounding wiring layer MET2 is moved away from the contact window RC and the dummy contact window DRC, which reduces the supply efficiency of AI necessary for the reaction between AI and Si in the contact area, and the reaction is further increased. becomes less likely to occur,
Contact resistance becomes more stable.

FIG. 7 is a partial plan view of another embodiment of the present invention, showing only the contact window RC and dummy contact window DRC. In the above embodiment, the dummy contact window DRC
was provided separately from the contact window RC,
As in this embodiment, the dummy contact window DRC may be integrated with the contact window RC. In other words, since the reaction between AI and Si at the edge portion 4, which substantially affects the contact resistance, should not proceed, the dummy contact window D is
It is sufficient that the diffusion of Si from the contact window RC toward the metal wiring layer MET2' is prevented by the diffusion of Si from the RC, and the shape of the dummy contact window DRC can be selected as appropriate.

As explained above, according to the present invention, it is possible to accurately design a resistor in which there is almost no variation in contact resistance and in which the actual resistance value (diffusion resistor contact resistance) hardly changes. It is extremely effective when applied to circuits with strict requirements.

[Brief explanation of drawings]

Figure 1 is a general current mirror circuit, Figure 2 is a plan view of a conventional design pattern, Figure 3 is a partial plan view of Figure 2,
4 is a sectional view along line xx' in FIG. 3, FIG. 5 is a plan view of an embodiment of the present invention, FIG. 6 is a sectional view taken along YY' in FIG. FIG. 6 is a partial plan view of another embodiment of the invention. In the figure, l, 2: semiconductor substrate, RED: diffusion layer (resistance diffusion layer), RC: contact window, DRC: dummy contact window, 3: insulating layer, METI, MET2. MET2'
, DMT: Metal wiring layer Figure 1 Figure 2 Figure 2 Figure 2

Claims (1)

[Claims] (1) A step of forming a diffusion layer of an opposite conductivity type on the surface of a semiconductor substrate of one conductivity type made of silicon, a step of forming an insulating layer on the diffusion layer, and a step of forming one of the diffusion layers on the insulating layer. forming a contact window exposing a portion of the contact window and a dummy contact window adjacent thereto; connecting the contact window and the dummy contact window;
And between the contact window and the dummy contact window,
forming a first metal wiring layer on the insulating layer having a thin line portion configured to be narrower than the width of both windows; forming a second metal wiring layer connected to the first metal wiring layer; and diffusing silicon of the substrate into the thin wire portion of the first metal wiring layer through the contact window and the dummy contact window. A method for manufacturing a semiconductor device, comprising: a heat treatment step for substantially saturating the semiconductor device.