JPS6352783B2 - - Google Patents

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Publication number
JPS6352783B2
JPS6352783B2 JP2882083A JP2882083A JPS6352783B2 JP S6352783 B2 JPS6352783 B2 JP S6352783B2 JP 2882083 A JP2882083 A JP 2882083A JP 2882083 A JP2882083 A JP 2882083A JP S6352783 B2 JPS6352783 B2 JP S6352783B2
Authority
JP
Japan
Prior art keywords
resistance
ratio
resistor
corners
resistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP2882083A
Other languages
Japanese (ja)
Other versions
JPS59155163A (en
Inventor
Atsushi Kishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP2882083A priority Critical patent/JPS59155163A/en
Publication of JPS59155163A publication Critical patent/JPS59155163A/en
Publication of JPS6352783B2 publication Critical patent/JPS6352783B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802Resistors only

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は、特に半導体集積回路における拡散抵
抗に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a diffused resistor in a semiconductor integrated circuit.

半導体集積回路の抵抗はその絶対精度よりむし
ろ抵抗の比精度を要求される場合が多い。本発明
は抵抗の良い比精度を得る事を目的としたもので
ある。以下、比精度を相対比と呼び、又抵抗の比
を抵抗比と呼ぶ。
Resistors in semiconductor integrated circuits are often required to have relative accuracy rather than absolute accuracy. The object of the present invention is to obtain good resistance ratio accuracy. Hereinafter, the ratio accuracy will be referred to as a relative ratio, and the ratio of resistances will be referred to as a resistance ratio.

本発明を説明する前に拡散抵抗について簡単に
ふれる。拡散抵抗は(1)式でその抵抗値Rが表わさ
れる。
Before explaining the present invention, we will briefly touch on diffused resistance. The resistance value R of the diffused resistance is expressed by equation (1).

R=RC+ρS・α・L/W+ρS/2・n ……(1) (1)式の右辺第1項、すなわち、RCは外部配線
と抵抗とのコンタクト部での抵抗値を示す。ま
た、ρSは拡散抵抗の層抵抗、αは抵抗幅の補正係
数、Lは拡散抵抗のマスク上の抵抗長、Wは拡散
抵抗のマスク上の抵抗幅、nは抵抗のコーナー数
(折り曲げ数)である。すなわち、半導体抵抗の
抵抗値は、電極との接触抵抗、抵抗領域の抵抗お
よび抵抗領域のコーナーの数できまる。
R=R CS・α・L/W+ρ S /2・n ...(1) The first term on the right side of equation (1), that is, R C is the resistance value at the contact part between the external wiring and the resistor. show. In addition, ρ S is the layer resistance of the diffused resistor, α is the correction coefficient for the resistance width, L is the resistance length on the mask of the diffused resistor, W is the resistance width on the mask of the diffused resistor, and n is the number of corners of the resistor (number of bends). ). That is, the resistance value of the semiconductor resistor is determined by the contact resistance with the electrode, the resistance of the resistance region, and the number of corners of the resistance region.

通常拡散抵抗は、バイポーラトランジスタを主
任とする集積回路では、NPNトランジスタのベ
ースと同時にP型不純物を導入し、熱工程を経て
形成される。ここで問題とするのは、この拡散抵
抗がコーナーを持ち、さらにコーナーを持つ他の
拡散抵抗と相対比をとる場合である。
In integrated circuits mainly using bipolar transistors, diffused resistors are usually formed by introducing P-type impurities into the base of an NPN transistor and performing a thermal process. The problem here is when this diffused resistor has a corner and takes a relative ratio with another diffused resistor that also has a corner.

一般に相対比をとる抵抗で誤差を生ずる主な原
因となるのは、抵抗コーナー部での拡散工程の拡
散横広がりによる抵抗長の変化、およびPR工程
でのアンダーエツチ、オーバーエツチ等による抵
抗長の変化である。尚、抵抗の電極とのコンタク
ト部での影響は、複数の抵抗同士で同じように受
けるものであるから無視できる。
In general, the main causes of errors in resistors that take relative ratios are changes in the resistance length due to lateral diffusion during the diffusion process at the corners of the resistance, and changes in the resistance length due to underetching, overetching, etc. in the PR process. It's a change. Note that the influence at the contact portion of the resistor with the electrode can be ignored since the plurality of resistors are affected in the same way.

第1図をもつて上記を簡単に説明する。(1)式よ
り、抵抗値、コーナー数等のパラメータを代入し
て求めた抵抗長L(L1+L2)はマスク上の寸法1
に相当する。P型不純物導入、熱工程を経た拡散
後の抵抗長は、コーナー部での拡散横広がり、エ
ツチング条件により拡散後では破線2で示すよう
になつてL′(L′1+L′2)となり設計値とズレてし
まつている。なお、抵抗幅の拡散前の値Wと拡散
後の値W′は(1)式でのα抵抗補正係数に含まれて
いる。このように、抵抗領域に折れ曲り部を有す
ることは、抵抗の設計値からのズレを大きくする
ものである。従つて、コーナー数の異なる二つの
抵抗の相対比を得るのは従来困難である。
The above will be briefly explained with reference to FIG. From equation (1), the resistance length L (L 1 + L 2 ) obtained by substituting parameters such as resistance value and number of corners is the dimension 1 on the mask.
corresponds to The resistance length after diffusion after introduction of P-type impurity and thermal process is L'(L' 1 + L' 2 ) as shown by broken line 2 due to the lateral spread of diffusion at the corner and etching conditions, and is designed as follows. It's out of sync with the value. Note that the value W of the resistance width before diffusion and the value W' after diffusion are included in the α resistance correction coefficient in equation (1). Thus, having a bent portion in the resistance region increases the deviation of the resistance from the designed value. Therefore, it has been difficult to obtain the relative ratio of two resistors having different numbers of corners.

相対比が要求される二つの抵抗パターンは、例
えば第2図のように従来は形成されていた。これ
ら二つの抵抗パターン3,4にはコーナーが存在
しないため、コーナー部でのエツチング条件によ
る拡散横広がりのために抵抗長が変化することは
無い。よつて抵抗比(1:2)の抵抗R1,R2
得るには、抵抗R2の抵抗長を抵抗R1のそれの2
倍にすればよい。
Two resistance patterns requiring a relative ratio have conventionally been formed as shown in FIG. 2, for example. Since there are no corners in these two resistor patterns 3 and 4, the resistance length does not change due to lateral spread of diffusion due to etching conditions at the corner portions. Therefore, to obtain resistors R 1 and R 2 with a resistance ratio (1:2), the resistance length of resistor R 2 is equal to 2 of that of resistor R 1 .
Just double it.

しかしながら、上記の方法では集積回路のチツ
プサイズの制約から実現できない場合が多い。す
なわち抵抗比が大きい抵抗の相対比をとる場合や
相対比をとる抵抗の数が多い場合では、すべての
抵抗領域を直線状に形成することは不可能に近
い。したがつて、抵抗領域は通常少なくとも1つ
のコーナーをもつ。したがつて、1以外の抵抗比
を実現するための従来の方法は、単に抵抗長をそ
の抵抗比に応じて設定するだけで、抵抗のコーナ
ー数は全く無視していた。抵抗のコーナー数は、
従来技術では抵抗配置スペースに合せて適当にも
うけており、抵抗幅のみ同一として抵抗長で相対
比をとつていた。
However, the above method is often not practical due to limitations on the chip size of the integrated circuit. That is, when a relative ratio of resistors having a large resistance ratio is taken, or when a large number of resistors have a relative ratio, it is almost impossible to form all the resistance regions in a straight line. Therefore, the resistive region usually has at least one corner. Therefore, the conventional method for realizing a resistance ratio other than 1 simply sets the resistance length according to the resistance ratio, and completely ignores the number of corners of the resistance. The number of corners of the resistor is
In the prior art, the resistors are provided appropriately according to the space for arranging the resistors, and the relative ratio is determined by the resistor length, assuming that only the resistor width is the same.

したがつて、コーナー部での拡散横広がり、エ
ツチング条件により相対比が正確にはとれていな
かつた。例えば、抵抗比1:10が望まれる二つの
抵抗R3,R4は、第3図に示すようなパターンと
されていた。抵抗R3,R4はマスク上で実線9,
11に示すパターン形状であり、これらの抵抗長
は1:10に設計されている。実質に不純物を導入
して領域を形成すると、破線10,12のように
変化する。また、抵抗R3,R4でコーナー数は共
に1である。
Therefore, due to the lateral spread of diffusion at the corners and the etching conditions, the relative ratio could not be accurately determined. For example, two resistors R 3 and R 4 for which a resistance ratio of 1:10 is desired have a pattern as shown in FIG. Resistors R 3 and R 4 are shown as solid lines 9 on the mask,
The pattern shape is shown in FIG. 11, and the resistance lengths of these resistors are designed to be 1:10. When impurities are substantially introduced to form a region, changes occur as shown by broken lines 10 and 12. Further, the number of corners is 1 for both resistors R 3 and R 4 .

このような構成において、抵抗R5の抵抗値は
(1)式より(2)式となり R5=RC+ρS/2+ρS・αL/W ……(2) となる。抵抗R6も(1)式より同様に示されるが、
コンタクト部抵抗RC、コーナー数1であるから
(3)式で示される。
In such a configuration, the resistance value of resistor R 5 is
From equation (1), equation (2) is obtained, and R 5 =R CS /2+ρ S ·αL/W ...(2). Resistance R 6 is also shown in the same way from equation (1), but
Since the contact part resistance R C has 1 corner,
It is shown by equation (3).

R6=10・R5=RC+ρS/2+ρS・α・10L+9・
R・W/ρS・α・9/2・W/α/W……(3) (3)式の右辺第3項の分子(10・L+9・RC
W/ρS・α+9/2・W/α)は、R5:R6=1:10のR
5 の抵抗長Lに対するR6の計算より求めた抵抗長
を意味する。
R 6 = 10・R 5 = R CS /2+ρ S・α・10L+9・
R・W/ρ S・α・9/2・W/α/W……(3) The numerator of the third term on the right side of equation (3) (10・L+9・R C
W/ρ S・α+9/2・W/α) is R5:R6=1:10
5 means the resistance length obtained from the calculation of R6 for the resistance length L.

ここで、実際に次に示す適当な数値を代入す
る。L=85μ、ρS=200Ω、RC=200Ω、α=1、
W=10μ、△L=5μ、△L/2はコーナーで生ずる 拡散横広がり、エツチング条件による抵抗長の変
化分である。マスク寸法上での抵抗比をR′4
R′3、拡散後の抵抗比をR4/R3とすると相対比K
はK=R4/R3/R′4/R′3で示される。
Here, actually substitute the following appropriate values. L=85μ, ρ S =200Ω, R C =200Ω, α=1,
W=10μ, ΔL=5μ, ΔL/2 is the lateral spread of diffusion occurring at the corner and the change in resistance length due to etching conditions. The resistance ratio on the mask dimensions is R′ 4 /
R′ 3 and the resistance ratio after diffusion is R 4 /R 3 , then the relative ratio K
is expressed as K=R 4 /R 3 /R' 4 /R' 3 .

K=R4/R3/R′4/R′3×100=105(%) ……(4) R4=RC+ρS/2+ρS・α・(10L+9W・RC/ρS
・α+9/2 W/α−△L)/W R′4=RC+ρS/2+ρS・α・(10L+9W・RC
ρS・α+9/2 W/α)/W R3=RC+ρS/2+ρS・α・(L−△L)/W R′3=RC+ρS/2+ρS・α・L/W (4)式は、抵抗設計値に対して拡散後のコーナー
での拡散横広がり、エツチング条件により抵抗の
相対比が5%ズレる事を示している。
K=R 4 /R 3 /R' 4 /R' 3 ×100=105 (%) ...(4) R 4 =R CS /2+ρ S・α・(10L+9W・R CS
・α+9/2 W/α−△L)/W R′ 4 = R CS /2+ρ S・α・(10L+9W・R C /
ρ S・α+9/2 W/α)/W R 3 =R CS /2+ρ S・α・(L−△L)/W R′ 3 =R CS /2+ρ S・α・L/W Equation (4) shows that the relative ratio of resistance deviates by 5% from the resistance design value due to the lateral spread of diffusion at the corner after diffusion and the etching conditions.

以上のように、従来技術では正確な相対比は実
現されなかつた。
As described above, an accurate relative ratio has not been achieved with the prior art.

本発明の目的は、正確な相対比をもつて形成さ
れた半導体抵抗を有する集積回路を提供すること
にある。
It is an object of the present invention to provide an integrated circuit having semiconductor resistors formed with precise relative ratios.

本発明は、相対比に応じて抵抗のコーナー数の
比も設定されていることを特徴とする。すなわ
ち、本発明は、相対比をとる抵抗の抵抗比に合せ
てコーナー数の比をとる事でコーナー部で生じる
拡散横広がり、エツチング条件での相対比の悪化
を防止するものであり、コーナー数さえ注意すれ
ば抵抗配置スペースにとらわれず抵抗の良好な相
対比を得るものである。
The present invention is characterized in that the ratio of the number of corners of the resistor is also set according to the relative ratio. That is, in the present invention, by setting the ratio of the number of corners in accordance with the resistance ratio of the resistor that takes the relative ratio, it is possible to prevent the diffusion lateral spread that occurs at the corner part and the deterioration of the relative ratio under etching conditions. If you are careful, you can obtain a good relative ratio of resistors regardless of the space in which the resistors are arranged.

第4図は本発明の一実施例を示すもので、第3
図と同様に抵抗比1:10を実現したものである。
ただし、抵抗R5に1つのコーナーがあるのに対
して、抵抗R6は10のコーナー数をもつように抵
抗領域が両端部間で10回折れ曲がつている。ま
た、抵抗R6の抵抗長は抵抗R5のそれに比して10
倍である。実線13,15は抵抗R5,R6のマス
ク上でのパターン図、破線14,16は実際に不
純物を導入して抵抗領域を形成した際にできるパ
ターン図である。
FIG. 4 shows one embodiment of the present invention.
As shown in the figure, a resistance ratio of 1:10 was achieved.
However, while resistor R 5 has one corner, resistor R 6 has 10 corners, so that the resistor region is bent 10 times between both ends. Also, the resistance length of resistor R 6 is 10% longer than that of resistor R 5 .
It's double. Solid lines 13 and 15 are pattern diagrams of the resistors R 5 and R 6 on the mask, and broken lines 14 and 16 are pattern diagrams formed when impurities are actually introduced to form a resistance region.

かかる抵抗パターンにおいて、第3図で示した
のと同じ数値(L=85μ、ρS=200Ω、RC=200
Ω、α=1、W=10μ、△L=5μ)を代入する
と、相対比Kは(5)式となる。
In such a resistance pattern, the same values as shown in FIG. 3 (L = 85μ, ρ S = 200Ω, R C = 200
Ω, α=1, W=10μ, ΔL=5μ), the relative ratio K becomes equation (5).

K=R6/R5/R′6/R′5×100=100(%) ……(5) R6=RC+5ρS+10L+9W・RC/ρS・α−△L・10/W R′6=RC+5ρS+10L+9・W・RC/W R5=RC+ρS/2+ρS・α・(L−△L)/W R′5=RC+ρS/2+ρS・α・L/W (5)式より拡散横広がり、エツチング条件によつ
ても良好な相対比を示す。
K=R 6 /R 5 /R' 6 /R' 5 ×100=100 (%) ...(5) R 6 = R C +5ρ S +10L+9W・R CS・α−△L・10/W R′ 6 = R C +5ρ S +10L+9・W・R C /W R 5 =R CS /2+ρ S・α・(L−△L)/W R′ 5 =R CS /2+ρ S・α・L/W Equation (5) shows a good relative ratio depending on the diffusion lateral spread and etching conditions.

第5図は本発明の他の実施例を示し、抵抗
R7:R8=1:2をねらつている。このため、抵
抗R7の抵抗領域5に対して抵抗R8の抵抗長を2
倍し、かつコーナー数も2倍にしている。ただ
し、抵抗R8は二つの抵抗領域6,8で形成され、
それらの間が配線導体7で接続されている。この
実施例でも、前述の理由から正確な相対比がえら
れる。
FIG. 5 shows another embodiment of the invention, in which a resistor
We are aiming for R 7 :R 8 =1:2. Therefore, the resistance length of resistor R8 is set to 2 for the resistance region 5 of resistor R7 .
The number of corners has also been doubled. However, resistance R 8 is formed by two resistance regions 6 and 8,
A wiring conductor 7 connects them. This example also provides accurate relative ratios for the reasons mentioned above.

以上の説明から一般式を導くと、 R1=RC+n1・ρS/2+ρS・α・L/W ……(6) R2/R1=n2/n1 ……(7) n1、n2:抵抗のコーナー数 (6)、(7)より相対比は(8)式となる。 Deriving the general formula from the above explanation, R 1 = R C + n 1・ρ S /2+ρ S・α・L/W …(6) R 2 /R 1 = n 2 /n 1 …(7) n 1 , n 2 : Number of corners of resistance From (6) and (7), the relative ratio is expressed as formula (8).

K=
RC+n2ρS/2+ρS・α・{(n2/n1L)+W(n2/n1
−1)RC/ρS・α−n2・△L}/WRC+n1ρS/2+ρ
S・αL−n1・△L/WRC+n2ρS/2+ρS・α・{(n
2/n1L)+W(n2/n1−1)RC/ρS・α/WRC+n1ρ
S/2+ρS・α・L/W ……(8) このように、本発明は要するにコーナー部で生
ずる誤差を抵抗比に合せコーナー数を設ける事で
相殺しているのである。
K=
R C +n 2 ρ S /2+ρ S・α・{(n 2 /n 1 L)+W(n 2 /n 1
−1) R CS・α−n 2・△L}/WR C +n 1 ρ S /2+ρ
S・αL−n 1・△L/WR C +n 2 ρ S /2+ρ S・α・{(n
2 /n 1 L) + W (n 2 /n 1 -1) R CS・α/WR C +n 1 ρ
S /2+ρ S・α・L/W (8) In this way, the present invention essentially cancels out the error occurring at the corner by providing the number of corners in accordance with the resistance ratio.

第6図は、レイアウトの関数でR9:R101:6
の抵抗比で、抵抗R9のコーナー数1カ所に対し
て抵抗R10のコーナー数6ケ所を一つの領域で実
現できない場合の例で、この場合、第5図に示し
たようにR10を2つの抵抗18,20を配線導体
19で接続したシリーズ接続体とし、合計のコー
ナー数が6となれば良い事で可能となる。
Figure 6 shows the layout function R 9 :R 10 1:6
This is an example of a case where six corners of resistance R 10 cannot be realized in one area with a resistance ratio of 1 corner of resistance R 9. In this case, R 10 is This is possible by forming a series connection body in which two resistors 18 and 20 are connected by a wiring conductor 19, and the total number of corners is six.

次に、抵抗比が整数倍でない場合のコーナー数
の設定について下記に述べる。
Next, the setting of the number of corners when the resistance ratio is not an integral multiple will be described below.

第1の方法は抵抗コーナー数が整数となる様最
少公倍数をとる方法である。具体的に一例を示す
とR1:R12=1kΩ:3.5kΩの場合、抵抗比に合せ
てコーナー数を設定するが、この場合1カ所対
3.5カ所となつてしまい不具合を生じる。この場
合、2を乗じて2:7すなわち、第7図に示すよ
うに、領域21,22のコーナー数2カ所対7カ
所とすれば良い。参考に次の数値W=10μ、RC
200Ω、α=1、L=85μ、△L=5μ、ρS=200Ω、
n1=2、n2=7を代入すると、抵抗領域形成後の
相対比は(8)式より K=R12/R11/R′12/R′11=100(%)……(
9) となり拡散後も良好な相対比がとれている。
The first method is to take the least common multiple so that the number of resistance corners becomes an integer. To give a specific example, in the case of R 1 : R 12 = 1kΩ : 3.5kΩ, the number of corners is set according to the resistance ratio, but in this case, one pair
There will be 3.5 locations and this will cause problems. In this case, the number of corners in the areas 21 and 22 may be 2 versus 7 by multiplying by 2 to 2:7, as shown in FIG. For reference, the following values W = 10μ, R C =
200Ω, α=1, L=85μ, △L=5μ, ρ S =200Ω,
Substituting n 1 = 2 and n 2 = 7, the relative ratio after forming the resistance region is obtained from equation (8): K = R 12 /R 11 /R' 12 /R' 11 = 100 (%)...
9), and a good relative ratio is obtained even after diffusion.

第2の方法はコーナー数を抵抗比に概略合せる
方法である。すなわち、例えばR13:R14=2.2k
Ω:8.2kΩの様な抵抗の相対比をとる場合、前述
の第1の方法でコーナー数が整数となる様にとる
と、R13でコーナー数11カ所、R14でコーナー数
41カ所となり、レイアウト上困難な場合が生じ
る。従つて、この様な場合では、概略コーナー数
を抵抗比に合せれば良い。すなわち、第8図に示
すように、R13の抵抗領域23に1カ所、R14
抵抗領域24に4カ所のコーナーをそれぞれ設け
ることで相対比がほぼ正確に実現される。
The second method is to roughly match the number of corners to the resistance ratio. That is, for example, R 13 :R 14 = 2.2k
When taking the relative ratio of resistances such as Ω: 8.2kΩ, if you use the first method described above to make the number of corners an integer, R 13 means 11 corners, and R 14 means 11 corners.
There will be 41 locations, and there will be some layout difficulties. Therefore, in such a case, it is sufficient to approximately match the number of corners to the resistance ratio. That is, as shown in FIG. 8, by providing one corner in the resistance region 23 of R 13 and four corners in the resistance region 24 of R 14 , the relative ratio can be realized almost accurately.

以上の通り、抵抗比に合せ抵抗のコーナー数の
比をとれば、抵抗の相対比は拡散、エツチング等
での抵抗長のズレ、コーナー部でのρSのバラツキ
に起因する相対比の悪化を防止でき精度の良い相
対比が得られる。
As mentioned above, if the ratio of the number of corners of the resistor is taken to match the resistance ratio, the relative ratio of the resistor will be reduced by the deterioration of the relative ratio due to the deviation of the resistor length due to diffusion, etching, etc., and the variation in ρ S at the corner part. This can be prevented and a highly accurate relative ratio can be obtained.

以上はP型不純物拡散抵抗で説明してきたが、
本願はイオン注入抵抗、ピンチ抵抗等の抵抗やN
型不純物による抵抗にも適応できる。
The above has been explained using P-type impurity diffused resistance,
This application deals with resistors such as ion implantation resistors, pinch resistors, etc.
It can also be applied to resistance due to type impurities.

一例としてピンチ抵抗の相対比1:3にとつた
場合を第9図に示す。ピンチ抵抗は、抵抗領域2
5の一部とオーバラツプする領域26を設け、領
域26下の抵抗領域25部分を高抵抗として使う
ものであるから、抵抗R15に対して抵抗R16では
領域28を領域29の3つのコーナー部とオーバ
ーラツプするように設ける。
As an example, FIG. 9 shows a case where the relative ratio of pinch resistance is 1:3. Pinch resistance is resistance area 2
A region 26 is provided that overlaps a part of the resistor region 5, and the portion of the resistor region 25 below the region 26 is used as a high resistance. It is provided so that it overlaps with the

以上のように、本発明は相対比をとる抵抗が多
い場合、又パワーIC等でのアイドリング設定用
抵抗など良い相対比が要求され、さらに抵抗比が
大きい場合などに好適である。すなわち、自由な
抵抗配置スペースで良好な相対比が得られる事か
ら半導体集積回路において高集積化に大いに役立
つ。
As described above, the present invention is suitable for cases where there are many resistances having relative ratios, or cases where a good relative ratio is required, such as a resistance for setting idling in a power IC, etc., and where the resistance ratio is large. That is, since a good relative ratio can be obtained with a free space for arranging the resistors, it is very useful for increasing the degree of integration in semiconductor integrated circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第3図は従来の半導体抵抗を示すパ
ターン平面図、第4図乃至第8図は本発明を拡散
抵抗に適用した実施例を示す抵抗のパターン図で
あり、第9図は本発明をピンチ抵抗に適用した実
施例を示す。 1,3,4,5,6,8,9,11,13,1
5,17,18,20,21,22,23,2
4,25,27……P型不純物マスク上の寸法領
域、7,19……接続用Al配線、2,10,1
2,14,16……拡散後のP型不純物抵抗領
域、26,27……N型不純物層をそれぞれ示
す。
1 to 3 are pattern plan views showing a conventional semiconductor resistor, FIGS. 4 to 8 are resistor pattern diagrams showing an embodiment in which the present invention is applied to a diffused resistor, and FIG. 9 is a pattern diagram showing the present invention. An example in which the invention is applied to a pinch resistance will be shown. 1, 3, 4, 5, 6, 8, 9, 11, 13, 1
5, 17, 18, 20, 21, 22, 23, 2
4, 25, 27...Dimensional area on P-type impurity mask, 7, 19... Al wiring for connection, 2, 10, 1
2, 14, 16: P-type impurity resistance regions after diffusion, 26, 27: N-type impurity layers, respectively.

Claims (1)

【特許請求の範囲】[Claims] 1 少なくとも第1および第2の半導体抵抗素子
を有し、前記第1および第2の抵抗素子のそれぞ
れの折り曲げ回数の比が前記第1および第2の抵
抗素子間の抵抗比と概略一致していることを特徴
とする半導体装置。
1 At least a first and second semiconductor resistance element is provided, and the ratio of the number of bends of each of the first and second resistance elements is approximately equal to the resistance ratio between the first and second resistance elements. A semiconductor device characterized by:
JP2882083A 1983-02-23 1983-02-23 Semiconductor device Granted JPS59155163A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2882083A JPS59155163A (en) 1983-02-23 1983-02-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2882083A JPS59155163A (en) 1983-02-23 1983-02-23 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS59155163A JPS59155163A (en) 1984-09-04
JPS6352783B2 true JPS6352783B2 (en) 1988-10-20

Family

ID=12259033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2882083A Granted JPS59155163A (en) 1983-02-23 1983-02-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59155163A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63142667A (en) * 1986-12-04 1988-06-15 Nec Corp Gaas semiconductor integrated circuit

Also Published As

Publication number Publication date
JPS59155163A (en) 1984-09-04

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