JPH0997876A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the error of the total resistance value of polycrystalline silicon resistors composed of polycrystalline silicon films and diffusion resistors composed of diffusion layers connected in series resulting from the error of the forming accuracy of the resistors by forming the diffusion resistors by introducing an impurity into a substrate by using the polycrystalline silicon resistors formed on an insulating film as a mask. SOLUTION: Diffusion resistors 41a are formed by implanting impurity ions into a substrate by using polycrystalline silicon resistors 31a as a mask. When the widths W1 of the resistors 31a become wider than a desired value, the widths W2 of the diffusion resistors 41a formed by using the resistors 31a as a mask become narrower unless the absolute forming area of the resistor elements 41a and 31a changes. Even when the widths W1 become narrower than the desired value and a error occurs in the forming accuracy of the resistors 31a and 41a, the sum of the widths W1 and W2 always become constant. Consequently, even when the cross-sectional areas of the resistors 31a decrease or increase due to the forming error, the cross-sectional areas of the resistors 41a which are used in paired states with the resistors 31a increase or decrease. Therefore, the total resistance value of the resistors 31a and 41a connected in series offsets the forming error and approaches a desired value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device having a resistance element used in a semiconductor integrated circuit and its manufacturing method.

[0002]

2. Description of the Related Art As a resistance element used in a semiconductor integrated circuit, a polycrystalline silicon resistor formed by introducing impurities into polycrystalline silicon formed in a predetermined width on an insulating film of a semiconductor substrate, or a semiconductor substrate There is a diffusion resistance formed by introducing an impurity with a predetermined width. The resistance values of these resistance elements are controlled by adjusting the concentration of impurities introduced into each of them and by adjusting the length, width and the like.

Next, a method of forming these conventional resistance elements will be briefly described. FIG. 3 is a cross-sectional view illustrating a method of manufacturing a polycrystalline silicon resistor. First, as shown in FIG. 3A, a silicon semiconductor substrate 111 is prepared. Next, an oxide film 112 is formed on the surface of the substrate 111 by a thermal oxidation method, a CVD method or the like. This oxide film 112 is the same as a gate oxide film or the like formed when manufacturing another semiconductor element such as a transistor on the substrate.

Then, as shown in FIG. 3B, the oxide film 1
Polycrystalline silicon 121 is formed on the surface 12 by the CVD method or the like. Next, a positive photoresist 122 is formed on the polycrystalline silicon 121, and the resist 122 is exposed using an exposure mask 123 that blocks the exposure light only at the portions where the polycrystalline silicon 121 remains.

Subsequently, as shown in FIG. 3C, the exposed resist 122 is developed to form a resist mask (not shown), and then the polycrystalline silicon 121 is etched by the RIE method using this resist mask. By removing the resist mask, a polycrystalline silicon resistor 131 having a predetermined pattern is formed on the oxide film 112. Subsequently, although not shown, after forming an interlayer insulating film on the substrate 111, a contact hole is formed in this interlayer insulating film, and an end portion of the polycrystalline silicon resistor 131 is wired by a conductive film. FIG. 4 is a cross-sectional view illustrating the method of manufacturing the diffused resistor.

First, as shown in FIG. 4A, an N type silicon semiconductor substrate 211 is prepared. This substrate 211 is
It may be an epitaxial layer or a buried layer. Next, a nitride film 212 is formed on the substrate 211 in the region where the diffusion resistance is formed. Then, heat treatment is performed to oxidize the substrate 211 other than the region where the nitride film 212 is formed, so that the element isolation oxide film 213 is formed. Next, the nitride film 212 is removed. This method is a general method called the LOCOS method. As a method of forming the element isolation oxide film, there is also a method of embedding an oxide film in the substrate 211.

Subsequently, as shown in FIG. 4B, the substrate 21 is formed using the element isolation insulating film 213 as a mask for ion implantation.
Ion implantation 221 of P-type impurities having a conductivity type opposite to that of the substrate 211 is performed from above. The ion implantation 221 may be performed simultaneously with ion implantation for forming an impurity region when manufacturing another semiconductor element on the substrate, such as a transistor.

Subsequently, as shown in FIG. 4C, heat treatment is performed to diffuse the impurities ion-implanted into the substrate 211 to form a diffusion resistor 231 having a conductivity type opposite to that of the substrate. Next, although not shown, after forming an interlayer insulating film on the substrate 211, a contact hole is formed in this interlayer insulating film, and the end portion of the diffusion resistor 131 is wired by a conductive film.

The manufacturing method described above has the following problems. In the manufacturing process of the polycrystalline silicon resistor, an error occurs in the width of the resist mask due to an error in processing accuracy such as exposure accuracy and development accuracy in the resist mask forming step. If the polycrystalline silicon is patterned using the resist mask having this error as a mask, an error occurs in the width, that is, the cross-sectional area of the formed polycrystalline silicon resistor itself, resulting in an error in the resistance value of the polycrystalline silicon resistor.

Also in the step of forming the diffusion resistance, in the step of forming the element isolation oxide film, the width between the element isolation oxide films, that is, the diffusion resistance formation region, is caused by an error in the processing accuracy of the nitride film used as an oxidation mask. There is an error in the width of. Further, since the element isolation oxide film is used as a mask for ion implantation, if it is difficult to accurately control the thickness of the element isolation oxide film due to the occurrence of the bird's peak, etc., it is introduced into the substrate. An error also occurs in the amount of impurities.
Therefore, an error occurs in the width of the diffusion resistance itself, that is, the cross-sectional area,
As a result, an error occurs in the resistance value of the diffusion resistance.

If an error occurs in the resistance value of the resistance element,
In some cases, a desired operation characteristic may not be obtained in an integrated circuit including the resistance element, or a malfunction may occur. Further, when forming a diffusion resistance, an element isolation oxide film or the like used as a mask for ion implantation is required, but in order to form a region for forming this element isolation oxide film and an element isolation oxide film. The number of steps of is increased.

In order to suppress the error in the resistance value due to the error in the width direction of these resistance elements, the width of the resistance element is increased,
There is a method of reducing the influence of an error in processing accuracy. However, according to this method, it is necessary to increase the cross-sectional area of the resistance element in order to obtain a constant resistance value, which causes an increase in chip area and cost. It will be.

[0013]

As described above, in the conventional method for manufacturing a polycrystalline silicon resistor or a diffused resistor,
Due to the error of the processing accuracy, mainly the width of these resistive elements,
That is, there is a problem that an error occurs in the cross-sectional area and an error occurs in the resistance value of the formed resistance element. Therefore, there is a method of increasing the cross-sectional area of the resistance element and reducing the influence of an error in the processing accuracy, but as a result, there is a problem that the chip area and the cost are increased.

[0014]

In order to solve the above problems, the present invention provides a semiconductor device manufacturing method as described below and a semiconductor device manufactured by this manufacturing method. is there. That is, a first conductivity type semiconductor substrate having adjacent first and second regions, a first insulating film formed on at least the semiconductor substrate of the first region, and formed on the first insulating film A first resistance film,
A second diffusion type first diffusion layer formed in the semiconductor substrate in the second region, and means for electrically connecting one ends of the first resistance film and the first diffusion layer to each other, There is provided a semiconductor device comprising a resistance element having the other end of the one resistance film and the other end of the first diffusion layer as input / output terminals. As a manufacturing method thereof, a step of forming an insulating film on the surface of the first region of the first conductivity type semiconductor substrate, a step of forming a resistance film on the surface of the insulating film, and a step of forming the resistance film on the semiconductor substrate using the resistance film as a mask. It has a step of introducing a second conductivity type impurity into the semiconductor substrate in the second region to form a diffusion layer, and a step of electrically connecting one end of the resistance film and one end of the diffusion layer. A method of manufacturing a semiconductor device is provided.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing method of an embodiment of the present invention will be described below with reference to sectional views and perspective views. First, as shown in FIG. 1A, a P-type silicon substrate 11 having an N well region 12 formed therein is prepared. Next, this board 1
Film thickness of 100 to 10 on one surface by thermal oxidation method or CVD method
An oxide film 13 of about 00 nm is formed. The oxide film 13
May be the same as another semiconductor element on the substrate 11, such as a gate oxide film formed when manufacturing a transistor or the like.

Subsequently, as shown in FIG. 1B, the oxide film 1
Polycrystalline silicon 21 having a film thickness of about 100 to 500 nm is formed on the surface by the CVD method or the like. Next, polycrystalline silicon 2
A positive type photoresist 22 is formed on the resist layer 1, and the resist 22 is exposed by using an exposure mask 23 that blocks the exposure light only in the portion where the polycrystalline silicon 21 remains. The width of the resist 22 exposed here is preferably approximately the same as the width of the portion where the polycrystalline silicon 21 is left. When forming a plurality of polycrystalline silicon resistors, it is desirable to form them in parallel.

Subsequently, as shown in FIG. 1C, the exposed resist 22 is developed to form a resist mask (not shown), and then the polycrystalline silicon 21 is etched by the RIE method using this resist mask. By removing the resist mask, a plurality of polycrystalline silicon resistors 31 having a predetermined width are formed on the oxide film 13. The width of the polycrystalline silicon resistor 31 is about 4 to 50 μm, and the length thereof is about 10 to 5000 μm.

Subsequently, as shown in FIG. 1D, the polycrystalline silicon resistor 31 is used as a mask for the substrate 11 and an impurity of a conductivity type opposite to that of the substrate 11, for example, B, is accelerated to energy 5 to 5.
Ion implantation is performed at 100 keV and a dose amount of 1E13 to 5E15 atoms ・ cm ^-3 . At this time, ion implantation is also performed into the polycrystalline silicon resistor 31.

Subsequently, as shown in FIG. 1 (e), a heat treatment is performed to form a diffusion resistance 41 in the region of the substrate 11 where the polycrystalline silicon resistance 31 is not formed on the surface. Through the above steps, the polycrystalline silicon resistor 31 is formed on the substrate 11, and the diffusion resistor 41 is formed in the substrate 11.

Subsequently, although not shown, an interlayer insulating film is formed on the substrate 11, and then a contact hole is formed in the interlayer insulating film or the interlayer insulating film and the oxide film 13 to adjoin one end of the polycrystalline silicon resistor 31. The conductive film is connected to one end of the diffused resistor 41 below the region to be formed.

Next, with reference to the top view of FIG. 2, the method of connecting the formed polycrystalline silicon resistor and the diffused resistor and the effect of the manufacturing method of the present invention and the semiconductor device manufactured by the method will be described. In FIG. 2, the same components as those in FIG. 1 are designated by the same reference numerals.

The resistance element of the present invention uses a pair of the polycrystalline silicon resistor 31 and the diffusion resistor 41 formed under the region adjacent to the polycrystalline silicon resistor 31. That is, the terminal 51 is formed at one end of the polycrystalline silicon resistor 31a, and the other end of the polycrystalline silicon resistor 31a and the diffusion resistor 4 are formed.
A terminal 52 electrically connects one end of 1a to a terminal 52, and a terminal 53 is formed at the other end of the diffused resistor 41a. Therefore, as the resistance element, the polycrystalline silicon resistance 31a and the diffusion resistance 4 are used.
1a is used by being connected in series. In addition to this,
A polycrystalline silicon resistor 31b adjacent to these resistors and a diffused resistor 41b connected in series with a terminal 55 are used by further connecting a terminal 53 and a terminal 54.
The resistance value of the resistance element formed by connecting adjacent polycrystalline silicon resistances or diffusion resistances in series can be arbitrarily selected at the design stage. In addition, these terminals 5
2 to 55 are formed by forming a contact hole in the interlayer insulating film and filling the contact hole with a conductive film.

The resistance element connected as described above has the following effects. According to the conventional manufacturing method, there is a problem that an error occurs mainly in the width of the resistance element, that is, a cross-sectional area, and an error occurs in the resistance value due to an error in processing accuracy. This is mainly due to the exposure accuracy and development accuracy of the photoresist. In the present invention, it is possible to reduce the error in the resistance value of the resistance element caused by the error in the processing accuracy due to these.

In FIG. 2, the width of the polycrystalline silicon resistor 31a in the horizontal direction in the drawing is W1, and the width of the diffusion resistor 41a in the horizontal direction in the drawing is W2. When a width error occurs in the resist mask when forming the polycrystalline silicon resistor, the error becomes the width error of the polycrystalline silicon resistor. That is, the width W1 of the polycrystalline silicon resistor may be widened or narrowed, and an error may occur with respect to the designed value. On the other hand, the diffusion resistance 41 is formed using the polycrystalline silicon resistance 31 as a mask for ion implantation. Therefore, if there is an error in the width W1 of the polycrystalline silicon resistor, naturally there is also an error in the width W2 of the diffusion resistor.

However, the width W1 of the polycrystalline silicon film
Becomes wider than a desired value, the width W2 of the diffused resistance formed using this as a mask becomes narrow unless the absolute area where these resistance elements are formed changes. On the contrary, when the width W1 of the polycrystalline silicon film becomes narrow, the width W2 of the diffusion resistance formed using this as a mask.
Becomes wider. That is, the value of the sum of W1 and W2 is always constant even if an error occurs in the processing accuracy.

Therefore, even if the cross-sectional area of the polycrystalline silicon resistor is decreased or increased due to an error in processing accuracy and the resistance value is increased or decreased from a desired value, the cross-sectional area of the diffusion resistor used in pair with this is increased or decreased. Since the resistance value decreases and the resistance value decreases or increases, the total resistance value of the pair of polycrystalline silicon films connected in series and the diffusion resistance cancels out the error in the processing accuracy, and becomes a desired value. You will get closer.

This effect becomes more remarkable as the resistance value per unit volume of the polycrystalline silicon resistance and the diffusion resistance approaches the same value. Further, even when these resistance values per unit volume are different, the effects shown above are obtained. Further, it is desirable to design the width of the polycrystalline silicon resistor and the width of the diffusion resistor to be equal.

When the resistivity of the polycrystalline silicon resistor per unit deposition is different from the resistivity of the diffusion resistor per unit deposition, the vertical length of the polycrystalline silicon resistor or part of the diffusion resistor is controlled. By doing so, the error due to the difference in resistivity can be reduced.

[0029]

According to the conventional manufacturing method, there is a problem that an error occurs mainly in the width of the resistance element, that is, in the cross-sectional area, and an error occurs in the resistance value due to an error in processing accuracy.
In the present invention, it is possible to reduce the error in the resistance value of the resistance element caused by the error in the processing accuracy resulting from these, and the resistance element used in the integrated circuit is accurately combined with the diffusion resistance and the polycrystalline silicon resistance. It can be formed by a combination. Therefore, problems such as malfunction of the integrated circuit due to deterioration of accuracy of the resistance element can be solved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing method of the present invention.

FIG. 2 is a top view illustrating a semiconductor device connection method and effects of the present invention.

FIG. 3 is a cross-sectional view illustrating a conventional method of manufacturing a resistance element.

FIG. 4 is a cross-sectional view illustrating a conventional method of manufacturing a resistance element.

[Explanation of symbols]

 11, 111 P-type silicon substrate 12 N-well region 13, 112 Oxide film 21, 121 Polycrystalline silicon 22, 122 Positive photoresist 23, 123 Exposure mask 31, 131 Polycrystalline silicon resistance 41, 231 Diffusion resistance 51, 52 , 53, 54, 55 Terminal 131 Resist mask 211 N-type silicon substrate 212 Nitride film 213 Element isolation oxide film 221 Ion implantation W1 Width of polycrystalline silicon resistance W2 Width of diffusion resistance

Claims (7)

[Claims] 1. A first conductivity type semiconductor substrate having adjacent first and second regions, a first insulating film formed on at least the semiconductor substrate in the first region, and a first insulating film on the first insulating film. The first resistance film formed, the second diffusion type first diffusion layer formed in the semiconductor substrate of the second region, the first resistance film and one end of the first diffusion layer electrically A semiconductor device comprising: a connecting element, and a resistance element having the other end of the first resistance film and the other end of the first diffusion layer as input / output terminals. 2. The semiconductor device according to claim 1, wherein the first and second regions are parallel to each other. 3. A semiconductor device, wherein the resistance film is made of polycrystalline silicon having impurities introduced therein. 4. A second insulating film having a third region adjacent to the second region, the second insulating film being formed on the semiconductor substrate in the third region, and the second resistor being formed on the second insulating film. A semiconductor device having a film. 5. A semiconductor device comprising a fourth region adjacent to the first region, and a second diffusion layer formed in the semiconductor substrate of the fourth region. 6. The semiconductor device according to claim 1, wherein the third or fourth region is parallel to the second or first region. 7. A step of forming an insulating film on the surface of the first region of the first conductivity type semiconductor substrate, a step of forming a resistive film on the surface of the insulating film, and a step of forming a resistive film on the semiconductor substrate using the resistive film as a mask. It has a step of introducing a second conductivity type impurity into the semiconductor substrate in the second region to form a diffusion layer, and a step of electrically connecting one end of the resistance film and one end of the diffusion layer. And a method for manufacturing a semiconductor device.