JPH04322458A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit device, by a master slice system, provided with a resistance-element array which restrains an irregularity in a characteristic and which has enhanced a utilization rate. CONSTITUTION:A semiconductor integrated circuit device is constituted by arranging islands 6 of resistance element arrays constituted of the following at the upper part and the lower part of arrangements of block frames 1 for analog circuit use in which transistor elements 2 and capacitor elements 3 have been arranged: resistance-element arrays 4 in which a plurality of resistance elements of the same size have been formed at definite intervals; and dummy resistance elements 7 formed on both ends of the arrays. Thereby, the electric characteristic of the resistance elements is made uniform, an irregularity in their specific accuracy is restrained and the utilization rate of the resistance elements can be enhanced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a master slice type semiconductor integrated circuit device for analog circuits.

0002

[Prior Art] In the conventional master slice method having blocks for analog circuits, blocks for analog circuits consisting of standardized transistor elements, capacitor elements, and resistance elements are arranged regularly on a chip as a master chip. 2. Description of the Related Art Master slice semiconductor integrated circuit devices using wiring formation masks designed according to various circuit designs are widely used.

FIG. 3 is a schematic plan view showing an example of a portion of a conventional master slice type semiconductor integrated circuit device in which analog circuit blocks are regularly arranged. In the figure, 1 is a block outer frame representing an analog circuit block, and inside the block outer frame 1 there are usually a transistor element 2, a capacitor element 3, and a resistor element 4-1.
, 4-2, . . . are provided in plural numbers. Note that 5 is a contact hole formed at both ends of the resistance elements 4-1, 4-2, . . . . By designing internal wiring using one or more of these unit blocks, various circuit blocks can be formed, and these are further defined as macroblocks, which can be used to create more advanced circuit blocks. Used as a group of blocks during implementation.

0004

[Problems to be Solved by the Invention] However, in the conventional master slice type semiconductor integrated circuit device described above, the resistance elements in the analog circuit blocks arranged as shown in FIG. 3 are similar to other transistor elements. are arranged in In FIG. 3, the resistance element array 4 is C-C'
A cross section along the line is shown in FIG. 4. Note that the line BB' indicates the center position of the resistor element array 4. In FIG. 4, 11 is a P type substrate, 12 is an N type buried layer provided on the substrate 11, 13 is an N type epitaxial layer formed on the buried layer 12, 14 is an N well, and 15 is an N type epitaxial layer formed on the buried layer 12.
is a P-type diffusion layer formed in the N-well 14, and is a P-type diffusion layer formed in the N-well 14;
-1, 4-2,... are configured. 16, 17
is a locos oxide film.

[0005] Each of the resistive elements 4-1, 4-2, . Set by conditions. However, in reality, in the resistance elements 4-1 and 4-4 at both ends of the resistance element array 4, the LOCOS oxide film 16 also has a step difference due to the step near the edge of the N-type buried layer 12.
Errors tend to occur in the resistance element width. In addition, near the B-B' line at the center of the resistor element row 4, the LOCOS oxide film 17 is almost over-etched than the designed value due to the influence of the resistor elements on both sides, and the resistor elements 4-1 and 4 at both ends are over-etched. -4 has a different degree of etching from other resistance elements. In this way, the resistance elements at both ends differ in the way the etching progresses, the way the diffusion spreads, the depth, etc. compared to the intermediate resistance element, resulting in a resistance value different from the designed value. Therefore, when designing an analog circuit that particularly requires specific accuracy of the resistor elements, there are disadvantages in that the positions of the resistor elements to be used are restricted and unnecessary resistor elements tend to be generated.

The present invention has been made in order to solve the above-mentioned problems of the conventional master slice type semiconductor integrated circuit device. An object of the present invention is to provide a slice-type semiconductor integrated circuit device.

[0007]

[Means and Operations for Solving the Problems] In order to solve the above problems, the present invention provides a master slice in which a plurality of analog circuit blocks each including at least one transistor element are regularly arranged on a semiconductor substrate. In this type of semiconductor integrated circuit device, a resistive element row in which a plurality of resistive elements of the same size are arranged at regular intervals is provided above and/or below the array of analog circuit blocks.

In this way, apart from the analog circuit block, by providing a resistive element array in which a plurality of resistive elements of the same size are arranged at regular intervals above and/or below the array of analog circuit blocks, It is possible to make the electrical characteristics of the resistive element uniform, thereby suppressing variations in relative accuracy, and to improve the utilization rate of the resistive element.

[0009]

[Example] Next, an example will be explained. FIG. 1 is a schematic plan view showing the configuration of an embodiment of a semiconductor integrated circuit device according to the present invention, and members that are the same as or correspond to those of the conventional device shown in FIG. There is. In the figure, reference numeral 6 denotes island portions of the resistor element array, which are arranged above and below the array of the frame 1 of the analog circuit block. ,...
A resistive element array 4 in which resistor elements are arranged at regular intervals, and dummy resistive elements 7 provided at both ends of the resistive element array 4 are arranged. Further, within the frame 1 of the analog circuit block, only the transistor element 2 and the capacitor element 3 are arranged.

A in the portion indicated by the dotted line 8 of the island portion 6 of the resistor element array of the semiconductor integrated circuit device constructed as described above.
A cross-sectional view taken along the line -A' is shown in FIG. In Figure 2,
Components that are the same as or equivalent to those shown in FIG. 4 are given the same reference numerals, and their explanations will be omitted. In addition, in FIG. 2, 15a
is a P-type diffusion layer constituting the dummy resistance element 7, and 18
is an oxide film formed on the surface.

Each resistive element of the resistive element array 4, which is constructed by arranging a plurality of resistive elements of the same size at regular intervals, is controlled by the manner in which etching progresses during the manufacturing process and the depth and spread of diffusion. They become equal, the electrical characteristics become uniform, and the accuracy of the resistance ratio improves. In other words, since the resistor element rows are formed on one N-type buried layer, ignoring the analog circuit block, the number of resistor elements placed near the edge of the N-type buried layer is reduced, and many A resistive element with high precision can be obtained. It goes without saying that by arranging the dummy resistive elements 7 at both ends of the resistive element array 4, the electrical characteristics of all the resistive elements of the resistive element array 4 are made uniform, and the accuracy of the resistance ratio is further improved.

Furthermore, the pitch of the resistive element in FIG.
(a+b) [n: integer, a: width of the P-type diffusion layer 15 constituting the resistance element, b: width of the LOCOS oxide film 17 between the resistance elements] of frame 1 of the analog circuit block including the transistor element. By matching the pitch d, it is possible to use an analog circuit as a macro cell in a macro block.

Further, in the above embodiment, the resistance element is formed of a P-type diffusion layer, but the resistance element can also be formed of a thin film resistor, and similar effects can be obtained.

[0014]

[Effect of the invention] As explained above based on the embodiments,
The present invention provides a resistor array in which multiple resistor elements of the same size are arranged at regular intervals in addition to the analog circuit block, so that the electrical characteristics of the resistor elements are made uniform and variations in ratio accuracy are suppressed. Therefore, it is possible to improve the utilization rate of the resistive element.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view showing an embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a diagram showing a cross section taken along line AA' in FIG. 1;

FIG. 3 is a schematic plan view showing a configuration example of a conventional semiconductor integrated circuit device.

FIG. 4 is a diagram showing a cross section taken along line CC' in FIG. 3;

[Explanation of symbols] 1. Analog circuit block frame 2 Transistor element 3 Capacitor element 4 Resistance element row 5 Contact hole 6 Island part of resistor element array 7 Dummy resistance element 15 P-type diffusion layer 16,17 Locos oxide film

Claims (3)

[Claims] 1. In a master slice type semiconductor integrated circuit device in which a plurality of analog circuit blocks each including at least one transistor element are regularly arranged on a semiconductor substrate, the upper part of the arrangement of the analog circuit blocks and Alternatively, a semiconductor integrated circuit device characterized in that a resistive element row in which a plurality of resistive elements of the same size are arranged at regular intervals is provided in the lower part. 2. The semiconductor integrated circuit device according to claim 1, wherein the resistance element is composed of a diffused resistance. 3. The semiconductor integrated circuit device according to claim 1, wherein the resistive element is composed of a thin film resistor.