JPS6042844A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase the integration density as a whole by a method wherein a plurality of low voltage circuit elements are collectively formed in a dielectric isolation island, when a high withstand voltage circuit element and the low voltage one are provided in a semiconductor substrate. CONSTITUTION:An n type Si island 37 for the high withstand voltage circuit element and an n type Si land 38 for the low withstand voltage one are formed in a supporter 43 via isolation oxide films 39 and 40, respectively; an n<+> type region 33 and a p type region 34 are formed in the island 37 by impurity diffusion from apertures provided in a surface oxide film 30, and further an n<+> type region is provided in the region 34. The island region 38 is put in the n-p-n three- layer structure of the region 38, a p type region 41, and n type regions 44 and 45 sandwiching a p type region 42, and an n<+> type region 32 and a p type region 31 are diffusion-formed in one region 44 p-n-isolated by means of the region 42, an n<+> type region being then provided in the region 31. Likewise, a p type region and n<+> type region 35 and 36 are provided in the other region 45, and all the low voltage circuit elements are contained in the Si island 38. In such a manner, the integration degree of the IC is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to a semiconductor integrated circuit having a dielectric isolation structure, and more particularly to a semiconductor integrated circuit in which a high voltage circuit element and a low voltage circuit element are simultaneously integrated. It is.

(2) Description of the Prior Art Conventionally, in this monkey semiconductor integrated circuit, as shown in FIG. In contrast, 11 silicon islands were required. Therefore, since a low voltage circuit element occupies a large capacity tRY on the board as a silicon island for accommodating the element, it is necessary to integrate the low voltage circuit element and the low voltage circuit element at the same time, which requires a large chip area. It had the disadvantage of being large.

(3) Purpose of the Invention The present invention solves the above-mentioned drawbacks by configuring a plurality of low-voltage circuit elements on one dielectric-isolated silicon island and separating the low-voltage circuit elements using PN junction isolation. The goal is to provide a semiconductor integrated circuit with high integration density.

(4) Structure of the Invention The present invention provides a support substrate in which a plurality of silicon island regions are provided through a dielectric film so that the main surface is exposed, and among the plurality of silicon island regions, the The silicon island region in which the breakdown voltage elements are provided is a single conductor, and the silicon island region in which the low breakdown voltage devices are provided consists of a silicon layer of a first conductivity type and a silicon layer of a second conductivity type in order from the main surface side. and a silicon layer of a first conductivity type, and an impurity of a second conductivity type is added from the main surface side into the silicon layer of the first conductivity type on the main surface side. By selectively diffusing , the first conductivity type silicon layer on the upper main surface side is separated into a plurality of silicon regions,
IIc! inside the silicon region of the first conductivity type and above the silicon island region where the high breakdown voltage element is provided! Impurities are superficially diffused on the surface side to form the desired circuit elements, and each element is connected to each other by metal interconnects and wires through holes provided in the surface oxide film covering the main surface. It is a semiconductor integrated circuit that has a % enemy.

(5) Examples Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows a sectional view of an embodiment of the present invention.

In this embodiment, single-crystal silicon islands 37 and 38 are provided in the support body 43 through isolation oxide films 39 and 40, and the silicon islands 37 are used for high voltage circuit elements, and impurities 33 and 34 etc., and spread the metal wirings 20 , 21 through the openings in the surface oxide film 30 .

. 22 constitutes a high voltage circuit element.

On the other hand, the silicon island 38 is used for low-voltage circuit elements, and the island KP! The layer 41 of NPN is a 31-dead structure, and the Pffi diffused from the surface oxide film side.
An impurity 42 is in contact with the P-type layer 41. This P
Impurities are diffused into the NWs 44 and 45 separated by the mold regions 41 and 42, and metal wirings 22 to 2 are formed through the openings in the surface oxide film.
By taking out 9, a low voltage circuit element is constructed. Moreover, since the wiring 26 in contact with the P-type diffusion region 42 is connected to the lowest potential point in the circuit, the low voltage circuit elements are insulated from each other.

As explained above, in a semiconductor integrated circuit in which high-voltage circuit elements and low-voltage circuit elements coexist, integration is possible by configuring a plurality of low-voltage circuit elements on one dielectric isolation island. The degree can be increased.

Next, an example of a method for manufacturing the semiconductor integrated circuit shown in FIG. 2 is shown in FIGS. 3(a) to 3(C)K. FIG. 3(a) A dielectric isolation substrate having KNW islands as shown in K is prepared, and the entire surface except the surface of the island 570 on which the low voltage circuit element is formed is covered with an oxide film 51. Etching liquid Kj etches the single crystal silicon in the island 57, but the etching is stopped at a certain depth without etching all the single crystal silicon in the island.

Next, using the oxide film 51 as a mask, P-type impurities are diffused to form a P-type layer 53. Next, as shown in FIG. 3(b), a KN type epitaxial layer 59 is formed on the surface of the substrate, and the substrate is polished from the surface to the position shown by the dashed line A--A. Next, as shown in FIG. 3(C), impurities 71 to 77 are diffused from the substrate surface. Form.

Next, openings are provided in the surface oxide film 70, and metal wirings 60-69 are formed in ohmic contact with the impurity diffusion regions 71-77 through the openings.

(6) Effects of the Invention As explained above, the present invention has the following advantages: 'In a semiconductor integrated circuit in which high-voltage circuit elements and low-voltage circuit elements are mixed, a plurality of low-voltage circuit elements are arranged on one dielectric isolation island. By forming this, it is possible to increase the cost efficiency of the semiconductor multiplication circuit.

[Brief explanation of the drawing]

Figure 1 is a sectional view showing a 5-dimensional example of the conventional technology;
The figure is a cross-sectional view showing one embodiment of the present invention, and Figure 3 is (=j
〜(C1 is a diagram showing the manufacturing process of the implementation row shown in FIG. 2. In the figures, 1 to 6, 20 to 29, 60 to 69, etc.
...metal wiring, 8.12.37.38.56°57
・・・・・・Single crystal silicon island, 13, 14, 39°4
0.54.55...Isolation oxide film, 7, 9,
10°11.3.1~36.41.42,53.71~
77... Impurity diffusion region, 15,43.58.
...Support, 16,30,51.70...
a surface oxide film, 52... a portion from which single crystal silicon has been removed by etching, and 59... an epitaxial layer.

Claims (1)

[Claims] Multiple surfaces exposed throughout the life through the fat electrolyte membrane in the supporting substrate? +nl silicon island region is provided, and among the silicon island regions of the axis number system, the silicon island region where the single-voltage element is provided is of a single conductivity type, and the silicon island region where the low breakdown voltage element is provided is of the single conductivity type. , in order from the main surface side, a first conductivity type silicon layer and a second conductivity type silicon layer;
Further, a three-layer silicon layer consisting of a silicon layer of a first conductivity type is provided, and an impurity of a second conductivity type is selected from the main surface side in the silicon layer of the first conductivity type on the main surface side. Accordingly, the first conductivity type silicon layer on the main surface side is separated into a plurality of silicon layers, and the silicon layer in the first conductivity type silicon region and the silicon where the high breakdown voltage element is provided are separated. Impurities are selectively diffused onto the main surface side of the island region to form a desired circuit element, and metal interconnections are formed between each element through holes provided in the surface oxide film forming the main surface. A semiconductor integrated circuit characterized by being connected by.