JPS5742170A - Field effect transistor - Google Patents

Abstract

PURPOSE:To obtain an FET with a high speed responsiveness, a large current layers and a high S/N ratio by laminating a plurality of semiconductor layers so alternately in such a manner as to be vertical thereto that the impurity concentration and the energy band gap are varied between the two. CONSTITUTION:An n type semiconductor layer 2 is formed on a half-insulating substrate 1. Here, the layer 2 is made up of a lamination of several semiconductor layers 6 and 7 which are arranged alternately in close contact while vertical to the substrate 1. A hetero junction 8 is yielded between the layers 6 and 7. In this arrangement, the impurity concentration and the energy band gap of the layer 7 are both made larger than those of the layer 6. A gate electrode 5 comprising a metal conductive layer 14 is mounted at the center of the upper surface of these laminates at the right angle thereto. On end of the laminate is packaged with an n<+> type layer and a metal conductive layer 11 is provided at the top thereof to make a source electrode 3. Likewise, the other end thereof is packaged with an n<+> type layer 12 and a conductor layer 13 is placed thereon to make a drain electrode 4.