JPS5615075A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5615075A
JPS5615075A JP9195879A JP9195879A JPS5615075A JP S5615075 A JPS5615075 A JP S5615075A JP 9195879 A JP9195879 A JP 9195879A JP 9195879 A JP9195879 A JP 9195879A JP S5615075 A JPS5615075 A JP S5615075A
Authority
JP
Japan
Prior art keywords
substrate
regions
closed loop
common
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9195879A
Other languages
Japanese (ja)
Inventor
Kunihiko Hirashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP9195879A priority Critical patent/JPS5615075A/en
Publication of JPS5615075A publication Critical patent/JPS5615075A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To suppress the parasitic capacity, inductance and resistance component and to obtain a satisfactory large current capacity characteristic of the semiconductor device by a method wherein plural field effect transistors are formed along closed loops on a semiconductor substrate, and respective electrodes are respectively connected in common. CONSTITUTION:On a main surface of the semiconductor substrate 1, drain regions 3a-3d reverse conductive to the substrate and are independent with each other are formed along the rectangular closed loop. Independent source regions 2a-2d confronting with the respective regions are provided along another rectangular closed loop surrounding that closed loop. Gate electrodes 4a-4d are formed and sticked on the substrate between those regions putting respectively gate insulating films between the substrate. The gate electrodes are connected in electrical common by gate electrode wirings 7-10, and respective source regions, respective drain regions are also connected respectively in common.
JP9195879A 1979-07-19 1979-07-19 Semiconductor device Pending JPS5615075A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9195879A JPS5615075A (en) 1979-07-19 1979-07-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9195879A JPS5615075A (en) 1979-07-19 1979-07-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5615075A true JPS5615075A (en) 1981-02-13

Family

ID=14041068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9195879A Pending JPS5615075A (en) 1979-07-19 1979-07-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5615075A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59144173A (en) * 1983-02-07 1984-08-18 Seiko Epson Corp Pattern shape of mosfet
US4684967A (en) * 1984-05-04 1987-08-04 Integrated Logic Systems, Inc. Low capacitance transistor cell element and transistor array
EP0248270A2 (en) * 1986-06-06 1987-12-09 Siemens Aktiengesellschaft Logic circuit
JPS634683A (en) * 1986-06-25 1988-01-09 Toshiba Corp Field-effect transistor
JPH03167879A (en) * 1989-11-28 1991-07-19 Nissan Motor Co Ltd Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51116682A (en) * 1975-04-07 1976-10-14 Hitachi Ltd Field effect transistor of high dielectric strength
JPS53141583A (en) * 1977-05-16 1978-12-09 Nec Corp Integrated-circuit semiconductor device of field effect type

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51116682A (en) * 1975-04-07 1976-10-14 Hitachi Ltd Field effect transistor of high dielectric strength
JPS53141583A (en) * 1977-05-16 1978-12-09 Nec Corp Integrated-circuit semiconductor device of field effect type

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59144173A (en) * 1983-02-07 1984-08-18 Seiko Epson Corp Pattern shape of mosfet
US4684967A (en) * 1984-05-04 1987-08-04 Integrated Logic Systems, Inc. Low capacitance transistor cell element and transistor array
EP0248270A2 (en) * 1986-06-06 1987-12-09 Siemens Aktiengesellschaft Logic circuit
JPS634683A (en) * 1986-06-25 1988-01-09 Toshiba Corp Field-effect transistor
JPH03167879A (en) * 1989-11-28 1991-07-19 Nissan Motor Co Ltd Semiconductor device

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