JPS574152A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS574152A JPS574152A JP7818880A JP7818880A JPS574152A JP S574152 A JPS574152 A JP S574152A JP 7818880 A JP7818880 A JP 7818880A JP 7818880 A JP7818880 A JP 7818880A JP S574152 A JPS574152 A JP S574152A
- Authority
- JP
- Japan
- Prior art keywords
- grounding wire
- circuits
- circuit
- signal
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dram (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55078188A JPS5840344B2 (ja) | 1980-06-10 | 1980-06-10 | 半導体記憶装置 |
EP81302502A EP0041844B1 (en) | 1980-06-10 | 1981-06-05 | Semiconductor integrated circuit devices |
DE8181302502T DE3175780D1 (en) | 1980-06-10 | 1981-06-05 | Semiconductor integrated circuit devices |
IE1262/81A IE52453B1 (en) | 1980-06-10 | 1981-06-08 | Semiconductor integrated circuit devices |
US06/272,367 US4439841A (en) | 1980-06-10 | 1981-06-10 | Semiconductor memory devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55078188A JPS5840344B2 (ja) | 1980-06-10 | 1980-06-10 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS574152A true JPS574152A (en) | 1982-01-09 |
JPS5840344B2 JPS5840344B2 (ja) | 1983-09-05 |
Family
ID=13654998
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55078188A Expired JPS5840344B2 (ja) | 1980-06-10 | 1980-06-10 | 半導体記憶装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4439841A (ja) |
EP (1) | EP0041844B1 (ja) |
JP (1) | JPS5840344B2 (ja) |
DE (1) | DE3175780D1 (ja) |
IE (1) | IE52453B1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59136948A (ja) * | 1983-01-18 | 1984-08-06 | エイ・ティ・アンド・ティ・コーポレーション | 集積回路チツプ |
JPH03133174A (ja) * | 1989-10-19 | 1991-06-06 | Toshiba Corp | 半導体記憶装置 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0079127A1 (en) * | 1981-11-06 | 1983-05-18 | Texas Instruments Incorporated | Programmable system component |
KR910008099B1 (ko) * | 1988-07-21 | 1991-10-07 | 삼성반도체통신주식회사 | 메모리 칩의 파워 및 시그널라인 버싱방법 |
US5378925A (en) * | 1990-07-23 | 1995-01-03 | Seiko Epson Corporation | Routing method and arrangement for power lines and signal lines in a microelectronic device |
JP2894635B2 (ja) * | 1990-11-30 | 1999-05-24 | 株式会社東芝 | 半導体記憶装置 |
GB2268332A (en) * | 1992-06-25 | 1994-01-05 | Gen Electric | Power transistor with reduced gate resistance and inductance |
JP2876963B2 (ja) * | 1993-12-15 | 1999-03-31 | 日本電気株式会社 | 半導体装置 |
DE69518973T2 (de) * | 1995-05-19 | 2001-02-22 | St Microelectronics Srl | Elektronische Schaltung mit mehreren Banddrähten, Herstellungsmethode und Testverfahren des Banddrahtzusammenhangs |
US7422930B2 (en) * | 2004-03-02 | 2008-09-09 | Infineon Technologies Ag | Integrated circuit with re-route layer and stacked die assembly |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3760384A (en) * | 1970-10-27 | 1973-09-18 | Cogar Corp | Fet memory chip including fet devices therefor and fabrication method |
US4122540A (en) * | 1974-03-18 | 1978-10-24 | Signetics Corporation | Massive monolithic integrated circuit |
-
1980
- 1980-06-10 JP JP55078188A patent/JPS5840344B2/ja not_active Expired
-
1981
- 1981-06-05 DE DE8181302502T patent/DE3175780D1/de not_active Expired
- 1981-06-05 EP EP81302502A patent/EP0041844B1/en not_active Expired
- 1981-06-08 IE IE1262/81A patent/IE52453B1/en not_active IP Right Cessation
- 1981-06-10 US US06/272,367 patent/US4439841A/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59136948A (ja) * | 1983-01-18 | 1984-08-06 | エイ・ティ・アンド・ティ・コーポレーション | 集積回路チツプ |
JPH0572744B2 (ja) * | 1983-01-18 | 1993-10-12 | At & T Technologies Inc | |
JPH03133174A (ja) * | 1989-10-19 | 1991-06-06 | Toshiba Corp | 半導体記憶装置 |
Also Published As
Publication number | Publication date |
---|---|
EP0041844A2 (en) | 1981-12-16 |
US4439841A (en) | 1984-03-27 |
EP0041844A3 (en) | 1983-06-15 |
IE811262L (en) | 1981-12-10 |
EP0041844B1 (en) | 1986-12-30 |
JPS5840344B2 (ja) | 1983-09-05 |
IE52453B1 (en) | 1987-11-11 |
DE3175780D1 (en) | 1987-02-05 |
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