DE69518973T2 - Elektronische Schaltung mit mehreren Banddrähten, Herstellungsmethode und Testverfahren des Banddrahtzusammenhangs - Google Patents

Elektronische Schaltung mit mehreren Banddrähten, Herstellungsmethode und Testverfahren des Banddrahtzusammenhangs

Info

Publication number
DE69518973T2
DE69518973T2 DE69518973T DE69518973T DE69518973T2 DE 69518973 T2 DE69518973 T2 DE 69518973T2 DE 69518973 T DE69518973 T DE 69518973T DE 69518973 T DE69518973 T DE 69518973T DE 69518973 T2 DE69518973 T2 DE 69518973T2
Authority
DE
Germany
Prior art keywords
ribbon
manufacturing
electronic circuit
wire connection
test method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69518973T
Other languages
English (en)
Other versions
DE69518973D1 (de
Inventor
Soldavini Francesco Chrappan
Alberto Salina
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69518973D1 publication Critical patent/DE69518973D1/de
Publication of DE69518973T2 publication Critical patent/DE69518973T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01037Rubidium [Rb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01088Radium [Ra]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
DE69518973T 1995-05-19 1995-05-19 Elektronische Schaltung mit mehreren Banddrähten, Herstellungsmethode und Testverfahren des Banddrahtzusammenhangs Expired - Fee Related DE69518973T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP95830214A EP0747930B1 (de) 1995-05-19 1995-05-19 Elektronische Schaltung mit mehreren Banddrähten, Herstellungsmethode und Testverfahren des Banddrahtzusammenhangs

Publications (2)

Publication Number Publication Date
DE69518973D1 DE69518973D1 (de) 2000-11-02
DE69518973T2 true DE69518973T2 (de) 2001-02-22

Family

ID=8221928

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69518973T Expired - Fee Related DE69518973T2 (de) 1995-05-19 1995-05-19 Elektronische Schaltung mit mehreren Banddrähten, Herstellungsmethode und Testverfahren des Banddrahtzusammenhangs

Country Status (4)

Country Link
US (1) US5909034A (de)
EP (1) EP0747930B1 (de)
JP (1) JPH0927528A (de)
DE (1) DE69518973T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008005203B4 (de) 2007-02-12 2019-03-28 Ic - Haus Gmbh Integrierter Pegelanpassungsbaustein mit integrierter Anschlussüberwachung

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Publication number Priority date Publication date Assignee Title
FR2769131B1 (fr) * 1997-09-29 1999-12-24 St Microelectronics Sa Dispositif semi-conducteur a deux plots de connexion de masse relies a une patte de connexion de masse et procede pour tester un tel dispositif
DE19825009C1 (de) * 1998-06-04 1999-11-25 Siemens Ag Prüfanordnung für Bondpad
JP2000021939A (ja) * 1998-06-29 2000-01-21 Mitsubishi Electric Corp 突起電極付半導体チップおよびその検査方法
FI990375A (fi) 1999-02-22 2000-12-07 Nokia Networks Oy Menetelmä piirilevykiinnitysten testaamiseksi ja piirilevy
US6987383B2 (en) * 2000-02-10 2006-01-17 Matsushita Electric Industrial Co., Ltd. Semiconductor device having a connection inspecting circuit for inspecting connections of power source terminals and grounding terminals, and inspection method for the same
GB0030346D0 (en) * 2000-12-13 2001-01-24 Mitel Semiconductor Ltd Integrated circuit test structure
DE10102000B4 (de) * 2001-01-18 2004-04-08 Infineon Technologies Ag Integrierte Schaltung mit Erkennungsschaltung und Verfahren zum Überprüfen einer Anschlusssituation eines Bondpads
DE60214746T2 (de) * 2001-05-23 2007-12-06 Koninklijke Philips Electronics N.V. Testschaltung
US7304393B1 (en) * 2004-03-24 2007-12-04 Microtune (Texas), L.P. System and method for coupling internal circuitry of an integrated circuit to the integrated circuit's package pins
DE102005004608B3 (de) * 2005-02-01 2006-04-20 Siemens Ag Verfahren und Schaltungsanordnung zum Überprüfen von elektrischen Kontaktierungen zwischen einem ersten Ausgangspin eines ersten Leistungsschalters einer Leistungsschaltvorrichtung und einem externen Knoten
JP5151021B2 (ja) * 2005-10-19 2013-02-27 富士電機株式会社 電力用半導体素子の異常検出装置
US7737715B2 (en) * 2006-07-31 2010-06-15 Marvell Israel (M.I.S.L) Ltd. Compensation for voltage drop in automatic test equipment
JP4804304B2 (ja) * 2006-10-11 2011-11-02 三菱電機株式会社 半導体装置
JP2009092529A (ja) * 2007-10-10 2009-04-30 Elpida Memory Inc 半導体回路およびその検査方法
US20110140730A1 (en) * 2008-05-30 2011-06-16 Nxp B.V. Detection circuitry for detecting bonding conditions on bond pads
KR102127892B1 (ko) * 2013-06-03 2020-06-29 삼성전자주식회사 와이어 본딩 기계의 동작 조건 오류 검출 방법 및 이를 수행하기 위한 장치

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* Cited by examiner, † Cited by third party
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JPS5840344B2 (ja) * 1980-06-10 1983-09-05 富士通株式会社 半導体記憶装置
JPS5772349A (en) * 1980-10-23 1982-05-06 Nec Corp Semiconductor integrated circuit device
JPH01154546A (ja) * 1987-12-10 1989-06-16 Fujitsu Ltd 端子開放検出回路半導体装置
US4979016A (en) * 1988-05-16 1990-12-18 Dallas Semiconductor Corporation Split lead package
JPH04157747A (ja) * 1990-10-19 1992-05-29 Fujitsu Ltd リード線ボンディング良否判定試験用回路内蔵半導体集積回路
US5101154A (en) * 1990-11-13 1992-03-31 Motorola, Inc. Open bond detector for an integrated circuit
JPH0760838B2 (ja) * 1990-11-13 1995-06-28 株式会社東芝 半導体装置
JPH04199673A (ja) * 1990-11-29 1992-07-20 Oki Electric Ind Co Ltd 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008005203B4 (de) 2007-02-12 2019-03-28 Ic - Haus Gmbh Integrierter Pegelanpassungsbaustein mit integrierter Anschlussüberwachung

Also Published As

Publication number Publication date
US5909034A (en) 1999-06-01
EP0747930B1 (de) 2000-09-27
EP0747930A1 (de) 1996-12-11
DE69518973D1 (de) 2000-11-02
JPH0927528A (ja) 1997-01-28

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