JPS5740959A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5740959A
JPS5740959A JP55117503A JP11750380A JPS5740959A JP S5740959 A JPS5740959 A JP S5740959A JP 55117503 A JP55117503 A JP 55117503A JP 11750380 A JP11750380 A JP 11750380A JP S5740959 A JPS5740959 A JP S5740959A
Authority
JP
Japan
Prior art keywords
layer
resist layer
underlaid
plating
electrolytic plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55117503A
Other languages
Japanese (ja)
Inventor
Manabu Watase
Michihiro Kobiki
Kazuaki Segawa
Takeshi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55117503A priority Critical patent/JPS5740959A/en
Publication of JPS5740959A publication Critical patent/JPS5740959A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13063—Metal-Semiconductor Field-Effect Transistor [MESFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To contrive an increase in adhesive strength, a reduction in thermal resistance, the improvement of reliability by improving the flatness of a multilayer plating layer, by narrowing the opening section of a surface mask layer for selective plating than the opening section of an underlaid mask layer. CONSTITUTION:A source electrode 3, a drain electrode, and a gate electrode are deposited and formed on the surface of an N type GaAs semiconductor layer 2 grown on a semi-insulation GaAs substrate 1 and a part on the source electrode 3 is left and the other part is coated with an underlaid resist layer 4, furthermore, an underlying metal layer 5 for electrolytic plating is formed. After that, a surface resist layer 6 having an opening is formed inside the level difference section of the underlaid resist layer 4 and the underlying metal 5 for electrolytic plating on the source electrode 3. After forming a thick plating layer 7 at the opening section of the surface resist layer 6 by an electrolytic plating method, the surface resist layer 6, the underlying metal layer 5 for electrolytic plating, and the underlaid resist layer 4 are successively removed.
JP55117503A 1980-08-25 1980-08-25 Manufacture of semiconductor device Pending JPS5740959A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55117503A JPS5740959A (en) 1980-08-25 1980-08-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55117503A JPS5740959A (en) 1980-08-25 1980-08-25 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5740959A true JPS5740959A (en) 1982-03-06

Family

ID=14713351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55117503A Pending JPS5740959A (en) 1980-08-25 1980-08-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5740959A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270253A (en) * 1986-01-27 1993-12-14 Mitsubishi Denki Kabushiki Kaisha Method of producing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270253A (en) * 1986-01-27 1993-12-14 Mitsubishi Denki Kabushiki Kaisha Method of producing semiconductor device

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