JPS5464482A - Manufacture for semiconductor device - Google Patents

Manufacture for semiconductor device

Info

Publication number
JPS5464482A
JPS5464482A JP13112777A JP13112777A JPS5464482A JP S5464482 A JPS5464482 A JP S5464482A JP 13112777 A JP13112777 A JP 13112777A JP 13112777 A JP13112777 A JP 13112777A JP S5464482 A JPS5464482 A JP S5464482A
Authority
JP
Japan
Prior art keywords
layer
wafer
substrate
heat sink
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13112777A
Other languages
Japanese (ja)
Inventor
Hironobu Hatakeyama
Takeshi Suzuki
Takashi Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13112777A priority Critical patent/JPS5464482A/en
Publication of JPS5464482A publication Critical patent/JPS5464482A/en
Pending legal-status Critical Current

Links

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE: To avoid the occurrence of bending and damage to wafer, even if the thickness of substrate is made thin to increase the performance, by forming the metal reinforcement layer of well shape to compensate the mechanical strength of wafer, on the electrode placed on one major plane of the semiconductor wafer.
CONSTITUTION: On N++ type GaAs substrate 1, N- type GaAs layer 2 and N+ GaAs layer 3 are formed by lamination into the GaAs wafer 4, and the plated heat sink 6 forming part on the layer 3 is covered with resist mask, and the reinforcement layer 14 of well shape consisting of Au, Ni or Cu is formed with selective plating. Next, etching is made by removing the mask and after making thin the thickness of the substrate 1, the first and second ohmic electrodes 5 and 8 are coated on the well frame on the substrate 1 and the layer 3. After that, the reinforcement layer 4 is covered with the resist mask 15 and the heat sink 6 is formed in the frame of the layer 4 with selective plating again. After removing the layer 4 with the diode mesa-etched for the wafer 4 and stud 12 is fitted to the heat sink 6.
COPYRIGHT: (C)1979,JPO&Japio
JP13112777A 1977-10-31 1977-10-31 Manufacture for semiconductor device Pending JPS5464482A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13112777A JPS5464482A (en) 1977-10-31 1977-10-31 Manufacture for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13112777A JPS5464482A (en) 1977-10-31 1977-10-31 Manufacture for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5464482A true JPS5464482A (en) 1979-05-24

Family

ID=15050606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13112777A Pending JPS5464482A (en) 1977-10-31 1977-10-31 Manufacture for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5464482A (en)

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