JPS5480675A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5480675A
JPS5480675A JP14829877A JP14829877A JPS5480675A JP S5480675 A JPS5480675 A JP S5480675A JP 14829877 A JP14829877 A JP 14829877A JP 14829877 A JP14829877 A JP 14829877A JP S5480675 A JPS5480675 A JP S5480675A
Authority
JP
Japan
Prior art keywords
layer
insulation
insulation layer
substrate
titanium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14829877A
Other languages
Japanese (ja)
Inventor
Hiroshi Tsuda
Yasunobu Oshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14829877A priority Critical patent/JPS5480675A/en
Publication of JPS5480675A publication Critical patent/JPS5480675A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To ensure completely the conductive pulse for gold plating, by forming the metallic layer at the step formed with the first insulation layer, second insulation layer or the other insulation layer with them with the same process as with the case of multi-layer electrode formation.
CONSTITUTION: In the semiconductor device having the semiconductor substrate 1, insulation construction having the first insulation layer 2 and second insulation layer 3 provided on the substrate 1, and multi-layer film metallic layer including the golden layers 10 and 13 not directly coupled with the substrate 1 bonded with the substrate 1 and reaching the insulation construction, titanium-platinum metal layer 12 formed at the same time as the titanium-platinum electrode metal layer with lift away method is provided at the step between the insulation layer 2 and the insulation layer 3 or the step of other insulation layers.
COPYRIGHT: (C)1979,JPO&Japio
JP14829877A 1977-12-09 1977-12-09 Semiconductor device Pending JPS5480675A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14829877A JPS5480675A (en) 1977-12-09 1977-12-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14829877A JPS5480675A (en) 1977-12-09 1977-12-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5480675A true JPS5480675A (en) 1979-06-27

Family

ID=15449642

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14829877A Pending JPS5480675A (en) 1977-12-09 1977-12-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5480675A (en)

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