JPS5368971A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5368971A
JPS5368971A JP14504776A JP14504776A JPS5368971A JP S5368971 A JPS5368971 A JP S5368971A JP 14504776 A JP14504776 A JP 14504776A JP 14504776 A JP14504776 A JP 14504776A JP S5368971 A JPS5368971 A JP S5368971A
Authority
JP
Japan
Prior art keywords
production
semiconductor device
recesses
filling
covering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14504776A
Other languages
Japanese (ja)
Inventor
Yorihiro Uchiyama
Ryoji Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14504776A priority Critical patent/JPS5368971A/en
Publication of JPS5368971A publication Critical patent/JPS5368971A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

Abstract

PURPOSE: To lower cost without using plating method or the like and make beam leads nearly flush to wafer surface by providing recesses in the beam lead forming portion of a semiconductor wafer, covering the entire surface with an insulation layer, filling a liquid or paste form conductive material within these recesses and heat treating this to form electrode layers.
COPYRIGHT: (C)1978,JPO&Japio
JP14504776A 1976-12-01 1976-12-01 Production of semiconductor device Pending JPS5368971A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14504776A JPS5368971A (en) 1976-12-01 1976-12-01 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14504776A JPS5368971A (en) 1976-12-01 1976-12-01 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5368971A true JPS5368971A (en) 1978-06-19

Family

ID=15376147

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14504776A Pending JPS5368971A (en) 1976-12-01 1976-12-01 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5368971A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5196377A (en) * 1990-12-20 1993-03-23 Cray Research, Inc. Method of fabricating silicon-based carriers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5196377A (en) * 1990-12-20 1993-03-23 Cray Research, Inc. Method of fabricating silicon-based carriers

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