JPS5739568A - Semiconductor integrated circuit memory - Google Patents

Semiconductor integrated circuit memory

Info

Publication number
JPS5739568A
JPS5739568A JP56095310A JP9531081A JPS5739568A JP S5739568 A JPS5739568 A JP S5739568A JP 56095310 A JP56095310 A JP 56095310A JP 9531081 A JP9531081 A JP 9531081A JP S5739568 A JPS5739568 A JP S5739568A
Authority
JP
Japan
Prior art keywords
mos
fet
integrated circuit
semiconductor integrated
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56095310A
Other languages
Japanese (ja)
Inventor
Yoshio Sakai
Osamu Minato
Toshiaki Masuhara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56095310A priority Critical patent/JPS5739568A/en
Publication of JPS5739568A publication Critical patent/JPS5739568A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To reduce the number of aluminum wires in a semiconductor integrated circuit memory by commonly using ground wires of adjacent two memory cells. CONSTITUTION:This memory is composed of MOS-FETs T1, T2 forming flip-flop, transfer gate MOS-FET T3, T4, a wording wire 1, a ground wire 2, data wires 3, 4 and common ground wire 2' of adjacent two memory cells, and the connection of the gate polycrystalline silicon layer 15 of one MOS-FET T2 to the drain diffused layer 13 of the other MOS-FET T1 is formed of the second polycrystalline silicon layer 20 formed via an interlayer insulating film 19.
JP56095310A 1981-06-22 1981-06-22 Semiconductor integrated circuit memory Pending JPS5739568A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56095310A JPS5739568A (en) 1981-06-22 1981-06-22 Semiconductor integrated circuit memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56095310A JPS5739568A (en) 1981-06-22 1981-06-22 Semiconductor integrated circuit memory

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP60103709A Division JPS6110273A (en) 1985-05-17 1985-05-17 Semiconductor ic memory

Publications (1)

Publication Number Publication Date
JPS5739568A true JPS5739568A (en) 1982-03-04

Family

ID=14134180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56095310A Pending JPS5739568A (en) 1981-06-22 1981-06-22 Semiconductor integrated circuit memory

Country Status (1)

Country Link
JP (1) JPS5739568A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6242443A (en) * 1985-08-20 1987-02-24 Fujitsu Ltd Semiconductor memory device
JPS62283643A (en) * 1986-05-02 1987-12-09 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Metallic contact system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6242443A (en) * 1985-08-20 1987-02-24 Fujitsu Ltd Semiconductor memory device
JPH0744227B2 (en) * 1985-08-20 1995-05-15 富士通株式会社 Semiconductor memory device
JPS62283643A (en) * 1986-05-02 1987-12-09 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Metallic contact system

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