JPS5723151A - Interruption processing system - Google Patents

Interruption processing system

Info

Publication number
JPS5723151A
JPS5723151A JP9780080A JP9780080A JPS5723151A JP S5723151 A JPS5723151 A JP S5723151A JP 9780080 A JP9780080 A JP 9780080A JP 9780080 A JP9780080 A JP 9780080A JP S5723151 A JPS5723151 A JP S5723151A
Authority
JP
Japan
Prior art keywords
psw
interruption
channel
loading
sends
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9780080A
Other languages
English (en)
Other versions
JPS6160468B2 (ja
Inventor
Yuji Oinaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9780080A priority Critical patent/JPS5723151A/ja
Publication of JPS5723151A publication Critical patent/JPS5723151A/ja
Publication of JPS6160468B2 publication Critical patent/JPS6160468B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP9780080A 1980-07-16 1980-07-16 Interruption processing system Granted JPS5723151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9780080A JPS5723151A (en) 1980-07-16 1980-07-16 Interruption processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9780080A JPS5723151A (en) 1980-07-16 1980-07-16 Interruption processing system

Publications (2)

Publication Number Publication Date
JPS5723151A true JPS5723151A (en) 1982-02-06
JPS6160468B2 JPS6160468B2 (ja) 1986-12-20

Family

ID=14201852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9780080A Granted JPS5723151A (en) 1980-07-16 1980-07-16 Interruption processing system

Country Status (1)

Country Link
JP (1) JPS5723151A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6789187B2 (en) * 2000-12-15 2004-09-07 Intel Corporation Processor reset and instruction fetches

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6789187B2 (en) * 2000-12-15 2004-09-07 Intel Corporation Processor reset and instruction fetches

Also Published As

Publication number Publication date
JPS6160468B2 (ja) 1986-12-20

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