JPS5799051A - Computer system - Google Patents

Computer system

Info

Publication number
JPS5799051A
JPS5799051A JP55174504A JP17450480A JPS5799051A JP S5799051 A JPS5799051 A JP S5799051A JP 55174504 A JP55174504 A JP 55174504A JP 17450480 A JP17450480 A JP 17450480A JP S5799051 A JPS5799051 A JP S5799051A
Authority
JP
Japan
Prior art keywords
processing section
data
cpu7
section
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55174504A
Other languages
Japanese (ja)
Inventor
Ichirou Touma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Engineering Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Priority to JP55174504A priority Critical patent/JPS5799051A/en
Publication of JPS5799051A publication Critical patent/JPS5799051A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Abstract

PURPOSE:To prevent system down caused by misoperation, by newly providing a line connection/disconnection device at a CPU side. CONSTITUTION:When the operator selects a line selection switch 31 and an interruption is given to a CPU7 with a line connection designating switch 5, a processing section B is started, and the processing section B sets an F1 of flags F1-FN corresponding to line selection switches 31-3N to ''1''. When interruption is given to the CPU7 with a line disconnection designation switch 6, the section B is started similarly and the flag F1 is set to 0 this time. On the other hand, data from CDT master stations 11-1N is inputted to a processing section A of the CPU7 via DXI/021-2N. After the processing section A fetches this data, it discriminates the said flag F1, and if it is at ''1'', the content is stored the j-th area of a memory RD1 and if ''0'', it is not stored. Thus, a pocessing section C making monitor control by using the reception data stored in memories RD1-RDN, discriminates the effective/ineffective data, allowing to execution/stop of processing.
JP55174504A 1980-12-12 1980-12-12 Computer system Pending JPS5799051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55174504A JPS5799051A (en) 1980-12-12 1980-12-12 Computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55174504A JPS5799051A (en) 1980-12-12 1980-12-12 Computer system

Publications (1)

Publication Number Publication Date
JPS5799051A true JPS5799051A (en) 1982-06-19

Family

ID=15979651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55174504A Pending JPS5799051A (en) 1980-12-12 1980-12-12 Computer system

Country Status (1)

Country Link
JP (1) JPS5799051A (en)

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