JPS5721857A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5721857A
JPS5721857A JP9720680A JP9720680A JPS5721857A JP S5721857 A JPS5721857 A JP S5721857A JP 9720680 A JP9720680 A JP 9720680A JP 9720680 A JP9720680 A JP 9720680A JP S5721857 A JPS5721857 A JP S5721857A
Authority
JP
Japan
Prior art keywords
aluminum
ion injection
type
layer
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9720680A
Other languages
Japanese (ja)
Inventor
Shizuo Sawada
Satoru Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9720680A priority Critical patent/JPS5721857A/en
Publication of JPS5721857A publication Critical patent/JPS5721857A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To eliminate the mismatching of an ion injection region with a storage electrode region in a manufacturing method for the channel stopper of an MOS type DRAM by forming the ion injection region and the electrode region by a self-aligning method. CONSTITUTION:A field oxidized film 21 is formed on the surface of a P type silicon substrate 20 to form the first gate oxidized film 22 of 400Angstrom thick, a polycrystalline silicon layer 23 of 3,000Angstrom thick is accumulated thereon, N type impurity is diffused in the layer 23, a photoresist film 24 is formed thereon, and a window is opened. Then ions are injected to form an N type ion injection layer 25, aluminum 26 is then accumulated in the thickness of 2,000Angstrom , the resist film 24 is removed, and the aluminum 26 thereon is lifted off. With the residual aluminum 26 as a mask it is etched, and the first storage gate electrode 27 is formed.
JP9720680A 1980-07-16 1980-07-16 Manufacture of semiconductor device Pending JPS5721857A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9720680A JPS5721857A (en) 1980-07-16 1980-07-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9720680A JPS5721857A (en) 1980-07-16 1980-07-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5721857A true JPS5721857A (en) 1982-02-04

Family

ID=14186138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9720680A Pending JPS5721857A (en) 1980-07-16 1980-07-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5721857A (en)

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