JPS5749250A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5749250A
JPS5749250A JP55124844A JP12484480A JPS5749250A JP S5749250 A JPS5749250 A JP S5749250A JP 55124844 A JP55124844 A JP 55124844A JP 12484480 A JP12484480 A JP 12484480A JP S5749250 A JPS5749250 A JP S5749250A
Authority
JP
Japan
Prior art keywords
layer
opening
width
film
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55124844A
Other languages
Japanese (ja)
Inventor
Kazuhiko Tsuji
Kaoru Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP55124844A priority Critical patent/JPS5749250A/en
Publication of JPS5749250A publication Critical patent/JPS5749250A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To prevent the production of a leakage between elements due to a defect by opening an insulating film of the surface of a substrate wider than a mask layer in the step of forming a channel stop region and reducing the width of an ion injection region smaller than the width of the opening. CONSTITUTION:In the step of, for example, an MOSFET, an oxidized film 12 is formed on the surface of a P type substrate 11, and a resist layer 13 is coated. Then, a hole 13a is opened at the layer 13 of an element isolating region, the oxidized film 12 of the lower layer is photographically etched excessively, and the width of the opening 12a of the film 12 is increased by 0.2mum or larger than the width of the opening 13a. With the layer 13 as a mask, B ion injection layer 14 is then formed, a field oxidized film 15 is then formed in the opening 12a to complete the channel stop region, and then the step of manufacturing an FET or the like is performed. Thus, wide field film can be formed of the ion injected layer 14 with large defects, thereby improving the characteristics by reducing the leakage between the elements.
JP55124844A 1980-09-09 1980-09-09 Manufacture of semiconductor device Pending JPS5749250A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55124844A JPS5749250A (en) 1980-09-09 1980-09-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55124844A JPS5749250A (en) 1980-09-09 1980-09-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5749250A true JPS5749250A (en) 1982-03-23

Family

ID=14895488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55124844A Pending JPS5749250A (en) 1980-09-09 1980-09-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5749250A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0450401A2 (en) * 1990-03-20 1991-10-09 Kabushiki Kaisha Toshiba Method of manufacturing non-volatile semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0450401A2 (en) * 1990-03-20 1991-10-09 Kabushiki Kaisha Toshiba Method of manufacturing non-volatile semiconductor memory device
US5208173A (en) * 1990-03-20 1993-05-04 Kabushiki Kaisha Toshiba Method of manufacturing non-volatile semiconductor memory device

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