JPS57211265A - Manufacture of bipolar type integrated circuit - Google Patents

Manufacture of bipolar type integrated circuit

Info

Publication number
JPS57211265A
JPS57211265A JP56096203A JP9620381A JPS57211265A JP S57211265 A JPS57211265 A JP S57211265A JP 56096203 A JP56096203 A JP 56096203A JP 9620381 A JP9620381 A JP 9620381A JP S57211265 A JPS57211265 A JP S57211265A
Authority
JP
Japan
Prior art keywords
sio2
layer
shaped
base
polycrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56096203A
Other languages
Japanese (ja)
Inventor
Koichi Kanzaki
Minoru Taguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56096203A priority Critical patent/JPS57211265A/en
Priority to US06/389,931 priority patent/US4539742A/en
Priority to DE19823223230 priority patent/DE3223230A1/en
Publication of JPS57211265A publication Critical patent/JPS57211265A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To improve the degree of integration of I<2>L by a method wherein an n<+> poly crystalline Si is etched in anisotropic form, a groove is formed to a lower Si substrate, a collector is shaped to a projecting section through diffusion from the n<+> polycrystalline Si, and a base connecting hole is formed only to a groove bottom. CONSTITUTION:An n epitaxial layer 103 is stacked to an n<+> buried layer 102 on a p type Si 101 and isolated by SiO2 104, and a p<-> base 105 is formed. An SiO2 106 is shaped selectively onto the n layer 103, the n<+> polycrystalline Si 108, CVD SiO2 109 and Si3N4 110 are laminated, a mask with three-layer structure is formed through patterning, and the grooves 107 with approximately 0.15-0.7mum depth are molded through anisotropic etching. SiO2 thick films 111a are formed to the side surfaces of the n<+> layers 108 and SiO2 thin-films 111b onto the n layer 103 and the p<-> base 105 through wet oxidation. B ions are implanted, As is diffused from p<+> bases 112 and the n<+> layers 108 through annealing, and the n<+> collectors 113 are shaped. The holes are bored to the bottoms of the grooves 107 by self-aligning through anisotropic etching and Al is evaporated, electrodes 114, 115 are formed and the I<2>L is completed. According to this constitution, the IC, which operates at extremely high speed and has the extremely high degree of integration, is obtained.
JP56096203A 1981-06-22 1981-06-22 Manufacture of bipolar type integrated circuit Pending JPS57211265A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP56096203A JPS57211265A (en) 1981-06-22 1981-06-22 Manufacture of bipolar type integrated circuit
US06/389,931 US4539742A (en) 1981-06-22 1982-06-18 Semiconductor device and method for manufacturing the same
DE19823223230 DE3223230A1 (en) 1981-06-22 1982-06-22 SEMICONDUCTOR DEVICE AND METHOD FOR THEIR PRODUCTION

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56096203A JPS57211265A (en) 1981-06-22 1981-06-22 Manufacture of bipolar type integrated circuit

Publications (1)

Publication Number Publication Date
JPS57211265A true JPS57211265A (en) 1982-12-25

Family

ID=14158711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56096203A Pending JPS57211265A (en) 1981-06-22 1981-06-22 Manufacture of bipolar type integrated circuit

Country Status (1)

Country Link
JP (1) JPS57211265A (en)

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