JPS57176587A - Semiconductor ram device - Google Patents
Semiconductor ram deviceInfo
- Publication number
- JPS57176587A JPS57176587A JP56061206A JP6120681A JPS57176587A JP S57176587 A JPS57176587 A JP S57176587A JP 56061206 A JP56061206 A JP 56061206A JP 6120681 A JP6120681 A JP 6120681A JP S57176587 A JPS57176587 A JP S57176587A
- Authority
- JP
- Japan
- Prior art keywords
- same time
- write
- control signal
- turn
- inversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
Landscapes
- Static Random-Access Memory (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56061206A JPS57176587A (en) | 1981-04-24 | 1981-04-24 | Semiconductor ram device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56061206A JPS57176587A (en) | 1981-04-24 | 1981-04-24 | Semiconductor ram device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57176587A true JPS57176587A (en) | 1982-10-29 |
JPH0315278B2 JPH0315278B2 (ko) | 1991-02-28 |
Family
ID=13164477
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56061206A Granted JPS57176587A (en) | 1981-04-24 | 1981-04-24 | Semiconductor ram device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57176587A (ko) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0143624A2 (en) * | 1983-11-25 | 1985-06-05 | Fujitsu Limited | Dynamic semiconductor memory device having divided memory cell blocks |
JPS60197995A (ja) * | 1984-03-21 | 1985-10-07 | Toshiba Corp | スタテイツク型ランダムアクセスメモリ |
EP0156896A1 (en) * | 1983-09-27 | 1985-10-09 | Advanced Micro Devices, Inc. | A memory circuit having a memory reset and recovery controller |
JPS61105793A (ja) * | 1984-10-26 | 1986-05-23 | Matsushita Electronics Corp | メモリ装置 |
JPS61136396U (ko) * | 1985-02-12 | 1986-08-25 | ||
JPS63183681A (ja) * | 1987-01-26 | 1988-07-29 | Nec Corp | 記憶装置 |
JPS63228490A (ja) * | 1987-03-18 | 1988-09-22 | Sony Corp | メモリ装置 |
US4890263A (en) * | 1988-05-31 | 1989-12-26 | Dallas Semiconductor Corporation | RAM with capability for rapid clearing of data from memory by simultaneously selecting all row lines |
JPH05182499A (ja) * | 1991-12-27 | 1993-07-23 | Nec Corp | 不揮発性半導体記憶装置 |
EP0581443A2 (en) * | 1992-07-14 | 1994-02-02 | Aptix Corporation | Memory cell with known state on power-up |
US5305263A (en) * | 1991-06-12 | 1994-04-19 | Micron Technology, Inc. | Simplified low power flash write operation |
US5402381A (en) * | 1991-06-06 | 1995-03-28 | Nec Corporation | Semiconductor memory circuit having bit clear and/or register initialize function |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5178939A (ko) * | 1974-12-30 | 1976-07-09 | Fujitsu Ltd | |
JPS5562588A (en) * | 1978-10-31 | 1980-05-12 | Matsushita Electric Ind Co Ltd | Semiconductor memory circuit |
-
1981
- 1981-04-24 JP JP56061206A patent/JPS57176587A/ja active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5178939A (ko) * | 1974-12-30 | 1976-07-09 | Fujitsu Ltd | |
JPS5562588A (en) * | 1978-10-31 | 1980-05-12 | Matsushita Electric Ind Co Ltd | Semiconductor memory circuit |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0156896A1 (en) * | 1983-09-27 | 1985-10-09 | Advanced Micro Devices, Inc. | A memory circuit having a memory reset and recovery controller |
EP0143624A2 (en) * | 1983-11-25 | 1985-06-05 | Fujitsu Limited | Dynamic semiconductor memory device having divided memory cell blocks |
US4744061A (en) * | 1983-11-25 | 1988-05-10 | Fujitsu Limited | Dynamic semiconductor memory device having a simultaneous test function for divided memory cell blocks |
JPS60197995A (ja) * | 1984-03-21 | 1985-10-07 | Toshiba Corp | スタテイツク型ランダムアクセスメモリ |
JPS61105793A (ja) * | 1984-10-26 | 1986-05-23 | Matsushita Electronics Corp | メモリ装置 |
JPS61136396U (ko) * | 1985-02-12 | 1986-08-25 | ||
JPS63183681A (ja) * | 1987-01-26 | 1988-07-29 | Nec Corp | 記憶装置 |
JPS63228490A (ja) * | 1987-03-18 | 1988-09-22 | Sony Corp | メモリ装置 |
US4890263A (en) * | 1988-05-31 | 1989-12-26 | Dallas Semiconductor Corporation | RAM with capability for rapid clearing of data from memory by simultaneously selecting all row lines |
US5402381A (en) * | 1991-06-06 | 1995-03-28 | Nec Corporation | Semiconductor memory circuit having bit clear and/or register initialize function |
US5305263A (en) * | 1991-06-12 | 1994-04-19 | Micron Technology, Inc. | Simplified low power flash write operation |
JPH05182499A (ja) * | 1991-12-27 | 1993-07-23 | Nec Corp | 不揮発性半導体記憶装置 |
EP0581443A2 (en) * | 1992-07-14 | 1994-02-02 | Aptix Corporation | Memory cell with known state on power-up |
EP0581443A3 (en) * | 1992-07-14 | 1995-04-19 | Aptix Corp | Memory cell with known status after power is switched on. |
Also Published As
Publication number | Publication date |
---|---|
JPH0315278B2 (ko) | 1991-02-28 |
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