JPS57134735A - Bus controller - Google Patents

Bus controller

Info

Publication number
JPS57134735A
JPS57134735A JP2116781A JP2116781A JPS57134735A JP S57134735 A JPS57134735 A JP S57134735A JP 2116781 A JP2116781 A JP 2116781A JP 2116781 A JP2116781 A JP 2116781A JP S57134735 A JPS57134735 A JP S57134735A
Authority
JP
Japan
Prior art keywords
cpu1
signal
common memory
execution
access request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2116781A
Other languages
Japanese (ja)
Inventor
Kimio Yamanaka
Mitsunori Hirayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2116781A priority Critical patent/JPS57134735A/en
Publication of JPS57134735A publication Critical patent/JPS57134735A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To control a bus so that access request of other CPUs can be achieved instantly after the execution of instructions, by outputting a bus control signal to exclusively possesses a common memory for the time required for the execution of instructions from the CPU. CONSTITUTION:Although a common memory access request signal REQ1 of a CPU1 is outputted as the same as conventional circuits, a common memory access request signal REQ2 of a CPU2 is outputted under the conditions of AND condition between an address coincidence signal RD2 and an access preparation signal RDY2 with an AND circuit 6 and absence of a bus control signal GUARD of CPU1 by an inhibition circuit 8. Thus, the CPU1 can exclusively possess a common memory M with the signal GUARD. The said signal GUARD is set according to the length of the instruction of the CPU1 to assure the common memory access time required for the execution of the instruction of the CPU1. Thus, when the access of the CPU1 is finished, the CPU2 is accessible.
JP2116781A 1981-02-13 1981-02-13 Bus controller Pending JPS57134735A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2116781A JPS57134735A (en) 1981-02-13 1981-02-13 Bus controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2116781A JPS57134735A (en) 1981-02-13 1981-02-13 Bus controller

Publications (1)

Publication Number Publication Date
JPS57134735A true JPS57134735A (en) 1982-08-20

Family

ID=12047349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2116781A Pending JPS57134735A (en) 1981-02-13 1981-02-13 Bus controller

Country Status (1)

Country Link
JP (1) JPS57134735A (en)

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