JPS57126154A - Lsi package - Google Patents

Lsi package

Info

Publication number
JPS57126154A
JPS57126154A JP56011594A JP1159481A JPS57126154A JP S57126154 A JPS57126154 A JP S57126154A JP 56011594 A JP56011594 A JP 56011594A JP 1159481 A JP1159481 A JP 1159481A JP S57126154 A JPS57126154 A JP S57126154A
Authority
JP
Japan
Prior art keywords
surface parts
wiring conductors
substrate
pads
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56011594A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6250981B2 (enrdf_load_stackoverflow
Inventor
Akihiro Dotani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56011594A priority Critical patent/JPS57126154A/ja
Publication of JPS57126154A publication Critical patent/JPS57126154A/ja
Publication of JPS6250981B2 publication Critical patent/JPS6250981B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP56011594A 1981-01-30 1981-01-30 Lsi package Granted JPS57126154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56011594A JPS57126154A (en) 1981-01-30 1981-01-30 Lsi package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56011594A JPS57126154A (en) 1981-01-30 1981-01-30 Lsi package

Publications (2)

Publication Number Publication Date
JPS57126154A true JPS57126154A (en) 1982-08-05
JPS6250981B2 JPS6250981B2 (enrdf_load_stackoverflow) 1987-10-28

Family

ID=11782228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56011594A Granted JPS57126154A (en) 1981-01-30 1981-01-30 Lsi package

Country Status (1)

Country Link
JP (1) JPS57126154A (enrdf_load_stackoverflow)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936949A (ja) * 1982-08-25 1984-02-29 Nec Corp マルチチツプパツケ−ジ
JPS6047496A (ja) * 1983-08-26 1985-03-14 日立化成工業株式会社 セラミツク基板
FR2558643A1 (fr) * 1984-01-23 1985-07-26 Nec Corp Substrat de cablage a couches multiples
JPS61172353A (ja) * 1985-01-28 1986-08-04 Nec Corp セラミツク多層基板
EP0632499A3 (en) * 1993-05-28 1995-03-29 Sumitomo Electric Industries Semiconductor device substrate.
WO1998044557A1 (de) * 1997-03-27 1998-10-08 Ppc Electronic Ag Mehrlagige leiterplatte für hohe spannungen und hohe ströme sowie verfahren zur herstellung einer solchen
JP2016530698A (ja) * 2013-08-29 2016-09-29 クアルコム,インコーポレイテッド 基板用の超微小ピッチおよび間隔相互配線

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01125678U (enrdf_load_stackoverflow) * 1988-02-12 1989-08-28
JPH02133374U (enrdf_load_stackoverflow) * 1989-04-12 1990-11-06

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS548976A (en) * 1977-06-22 1979-01-23 Nec Corp Lsi package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS548976A (en) * 1977-06-22 1979-01-23 Nec Corp Lsi package

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936949A (ja) * 1982-08-25 1984-02-29 Nec Corp マルチチツプパツケ−ジ
JPS6047496A (ja) * 1983-08-26 1985-03-14 日立化成工業株式会社 セラミツク基板
FR2558643A1 (fr) * 1984-01-23 1985-07-26 Nec Corp Substrat de cablage a couches multiples
JPS61172353A (ja) * 1985-01-28 1986-08-04 Nec Corp セラミツク多層基板
EP0632499A3 (en) * 1993-05-28 1995-03-29 Sumitomo Electric Industries Semiconductor device substrate.
US5682063A (en) * 1993-05-28 1997-10-28 Sumitomo Electric Industries, Ltd. Substrate for semiconductor device
WO1998044557A1 (de) * 1997-03-27 1998-10-08 Ppc Electronic Ag Mehrlagige leiterplatte für hohe spannungen und hohe ströme sowie verfahren zur herstellung einer solchen
CH690806A5 (de) * 1997-03-27 2001-01-15 Ppc Electronic Ag Mehrlagiger Leiterplattenkörper für hohe Spannungen und hohe Ströme sowie Verfahren zur Herstellung eines solchen Leiterplattenkörpers.
JP2016530698A (ja) * 2013-08-29 2016-09-29 クアルコム,インコーポレイテッド 基板用の超微小ピッチおよび間隔相互配線
JP2017195403A (ja) * 2013-08-29 2017-10-26 クアルコム,インコーポレイテッド 基板用の超微小ピッチおよび間隔相互配線

Also Published As

Publication number Publication date
JPS6250981B2 (enrdf_load_stackoverflow) 1987-10-28

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