JPS54131871A - Packaging of ic case - Google Patents

Packaging of ic case

Info

Publication number
JPS54131871A
JPS54131871A JP3915278A JP3915278A JPS54131871A JP S54131871 A JPS54131871 A JP S54131871A JP 3915278 A JP3915278 A JP 3915278A JP 3915278 A JP3915278 A JP 3915278A JP S54131871 A JPS54131871 A JP S54131871A
Authority
JP
Japan
Prior art keywords
case
substrate
constitution
packaging
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3915278A
Other languages
Japanese (ja)
Inventor
Susumu Shibata
Masaru Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP3915278A priority Critical patent/JPS54131871A/en
Publication of JPS54131871A publication Critical patent/JPS54131871A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To ensure the packaging of the IC case with high degree of both the heat dissipation and the adhesion without using the heat sink tower by connecting the IC case directly to the substrate via the metal. CONSTITUTION:Metalized layer 43 and 44 are provided to substrate 10 and IC case 11 respectively, and then layer 43 and 44 are adhered together via solder 02 or the like. In such constitution, the heat generated from IC chip 05 flows from the case to the substrate via the metalized layer and the solder. Substrate 10 features a large surface area and thus functions as the heat sink tower, cooling down the substrate if necessary. At the same time, the case is fixed to the substrate, and accordingly the length of lead wires 21-14 plus 33 can be shortened. As a result, the occupied area can be reduced for the IC case.
JP3915278A 1978-04-05 1978-04-05 Packaging of ic case Pending JPS54131871A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3915278A JPS54131871A (en) 1978-04-05 1978-04-05 Packaging of ic case

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3915278A JPS54131871A (en) 1978-04-05 1978-04-05 Packaging of ic case

Publications (1)

Publication Number Publication Date
JPS54131871A true JPS54131871A (en) 1979-10-13

Family

ID=12545126

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3915278A Pending JPS54131871A (en) 1978-04-05 1978-04-05 Packaging of ic case

Country Status (1)

Country Link
JP (1) JPS54131871A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224235A (en) * 1984-04-20 1985-11-08 Fujitsu Ltd Semiconductor device
US4554575A (en) * 1983-05-12 1985-11-19 Westinghouse Electric Corp. Low stress leadless chip carrier and method of assembly

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4554575A (en) * 1983-05-12 1985-11-19 Westinghouse Electric Corp. Low stress leadless chip carrier and method of assembly
JPS60224235A (en) * 1984-04-20 1985-11-08 Fujitsu Ltd Semiconductor device
JPH032348B2 (en) * 1984-04-20 1991-01-14 Fujitsu Ltd

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