JPS5685835A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5685835A
JPS5685835A JP16256079A JP16256079A JPS5685835A JP S5685835 A JPS5685835 A JP S5685835A JP 16256079 A JP16256079 A JP 16256079A JP 16256079 A JP16256079 A JP 16256079A JP S5685835 A JPS5685835 A JP S5685835A
Authority
JP
Japan
Prior art keywords
film
recess
covered
substrate
amorphous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16256079A
Other languages
Japanese (ja)
Inventor
Tsutomu Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16256079A priority Critical patent/JPS5685835A/en
Publication of JPS5685835A publication Critical patent/JPS5685835A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape

Abstract

PURPOSE:To obtain a buried type gate electrode in a semiconductor device by forming a recess on the surface of an Si substrate, covering the wall surface and the bottom surface with an insulating film, filling an electrode material therein and covering it with an insulating film. CONSTITUTION:An SiO2 film 24, an Si3N4 film 26 and a Pt film 28 are laminated on a p type Si substrate 22, are opened with a hole, a recess 30 is etched on the substrate, and scratches are formed on the ends of the laminated films. The surface of the recess is covered with an SiO2 film 32. It is effective if a p type impurity layer is formed beforehand under the film 32. Subsequently, impurity-added amorphous Si 34 is covered from a vertical direction. Then, Pi 28 is selectively etched with aqua regia, and the amorphous Si film 34 is lifted off. Successively, with the Si3N4 film as a mask it is thermally oxidized, and is covered with an SiO2 film 36. At this time the amorphous Si becomes a polysilicon (gate electrode) 38. When the films 26 and 24 are thereafter etched, a buried type MOS gate can be completed. According to this configuration, a buried type insulating gate having a flat surface can be simply formed accurately.
JP16256079A 1979-12-14 1979-12-14 Manufacture of semiconductor device Pending JPS5685835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16256079A JPS5685835A (en) 1979-12-14 1979-12-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16256079A JPS5685835A (en) 1979-12-14 1979-12-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5685835A true JPS5685835A (en) 1981-07-13

Family

ID=15756902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16256079A Pending JPS5685835A (en) 1979-12-14 1979-12-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5685835A (en)

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