JPS54146584A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS54146584A
JPS54146584A JP5514078A JP5514078A JPS54146584A JP S54146584 A JPS54146584 A JP S54146584A JP 5514078 A JP5514078 A JP 5514078A JP 5514078 A JP5514078 A JP 5514078A JP S54146584 A JPS54146584 A JP S54146584A
Authority
JP
Japan
Prior art keywords
film
drain
source
gate
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5514078A
Other languages
Japanese (ja)
Inventor
Masayuki Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5514078A priority Critical patent/JPS54146584A/en
Publication of JPS54146584A publication Critical patent/JPS54146584A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To reduce the short channel effect by utilizing the unevenness caused on the surface of the semiconductor substrate through the selective oxidation method to form the gate at the concave part and the drian and source at the convex part each and then reducing the protrusion of the depletion layer at the drain side. CONSTITUTION:Selective oxidation 12 is applied to Si substrate 1 via the double- layer mask of SiO2 and Si3N4, and then drain 2 and source 3 are formed by the opposite conducting diffusion to substrate 1. Then field oxide film 5 of several hundreds of Angstrom is provided on layer 2 and 3, and gate oxide film 4 is formed through the selective etching. Finally, Al electride 6 and 7 are formed after drilling the opening to film 5. With this method, gate film 4 secures the sam level as the drain and the source, and depletion layer 8 has reduced protrusion right under film 4 at the side of drain 2. And the characteristic deterioration can be lessened greatly for the short-channel MOSFET, thus obtaining a high-performance MOSIC. The edge angle phi of film 12 ddpends on the thickness of the foundation oxide film and the formation temperature of film 12. And the larger angle phi the more the characteristics or the forming accuracy increases for the device.
JP5514078A 1978-05-09 1978-05-09 Manufacture of semiconductor device Pending JPS54146584A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5514078A JPS54146584A (en) 1978-05-09 1978-05-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5514078A JPS54146584A (en) 1978-05-09 1978-05-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54146584A true JPS54146584A (en) 1979-11-15

Family

ID=12990464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5514078A Pending JPS54146584A (en) 1978-05-09 1978-05-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54146584A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2625044A1 (en) * 1987-12-18 1989-06-23 Commissariat Energie Atomique MOS TRANSISTOR WITH END OF GRID DIELECTRIC INTERFACE / SUBSTRATE SUBSTRATE AND METHOD FOR MANUFACTURING THE TRANSISTOR
EP0449418A2 (en) * 1990-02-26 1991-10-02 Advanced Micro Devices, Inc. Insulated gate field effect device with a curved channel and method of fabrication
WO1993003502A1 (en) * 1991-07-26 1993-02-18 Nippondenso Co., Ltd. Method of producing vertical mosfet
US5248893A (en) * 1990-02-26 1993-09-28 Advanced Micro Devices, Inc. Insulated gate field effect device with a smoothly curved depletion boundary in the vicinity of the channel-free zone
EP0615282A2 (en) * 1993-03-10 1994-09-14 Samsung Electronics Co., Ltd. Methods for making MOSFET's with drain separated from channel
US5508541A (en) * 1992-09-22 1996-04-16 Kabushiki Kaisha Toshiba Random access memory device with trench-type one-transistor memory cell structure
US6015737A (en) * 1991-07-26 2000-01-18 Denso Corporation Production method of a vertical type MOSFET
US6603173B1 (en) 1991-07-26 2003-08-05 Denso Corporation Vertical type MOSFET
EP1089330A3 (en) * 1999-09-30 2003-09-24 Zarlink Semiconductor Limited Lateral field effect transistor

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4939100A (en) * 1987-12-18 1990-07-03 Commissariat A L'energie Atomique Process for the production of a MIS transistor with a raised substrate/gate dielectric interface end
FR2625044A1 (en) * 1987-12-18 1989-06-23 Commissariat Energie Atomique MOS TRANSISTOR WITH END OF GRID DIELECTRIC INTERFACE / SUBSTRATE SUBSTRATE AND METHOD FOR MANUFACTURING THE TRANSISTOR
US5248893A (en) * 1990-02-26 1993-09-28 Advanced Micro Devices, Inc. Insulated gate field effect device with a smoothly curved depletion boundary in the vicinity of the channel-free zone
EP0449418A2 (en) * 1990-02-26 1991-10-02 Advanced Micro Devices, Inc. Insulated gate field effect device with a curved channel and method of fabrication
US5460985A (en) * 1991-07-26 1995-10-24 Ipics Corporation Production method of a verticle type MOSFET
WO1993003502A1 (en) * 1991-07-26 1993-02-18 Nippondenso Co., Ltd. Method of producing vertical mosfet
US6015737A (en) * 1991-07-26 2000-01-18 Denso Corporation Production method of a vertical type MOSFET
US6603173B1 (en) 1991-07-26 2003-08-05 Denso Corporation Vertical type MOSFET
US5508541A (en) * 1992-09-22 1996-04-16 Kabushiki Kaisha Toshiba Random access memory device with trench-type one-transistor memory cell structure
US5736760A (en) * 1992-09-22 1998-04-07 Kabushiki Kaisha Toshiba Random access memory device with trench-type one-transistor memory cell structure
EP0615282A2 (en) * 1993-03-10 1994-09-14 Samsung Electronics Co., Ltd. Methods for making MOSFET's with drain separated from channel
EP0615282A3 (en) * 1993-03-10 1996-12-11 Samsung Electronics Co Ltd Methods for making MOSFET's with drain separated from channel.
EP1089330A3 (en) * 1999-09-30 2003-09-24 Zarlink Semiconductor Limited Lateral field effect transistor

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