JPS5678122A - Formation of pattern - Google Patents

Formation of pattern

Info

Publication number
JPS5678122A
JPS5678122A JP15418779A JP15418779A JPS5678122A JP S5678122 A JPS5678122 A JP S5678122A JP 15418779 A JP15418779 A JP 15418779A JP 15418779 A JP15418779 A JP 15418779A JP S5678122 A JPS5678122 A JP S5678122A
Authority
JP
Japan
Prior art keywords
resin
pattern
resist
layer
resin layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15418779A
Other languages
Japanese (ja)
Inventor
Minoru Nakajima
Shiro Takeda
Toshisuke Kitakoji
Kyohei Murakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15418779A priority Critical patent/JPS5678122A/en
Publication of JPS5678122A publication Critical patent/JPS5678122A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To form a pattern having superior resolution in accordance with the design on a semiconductor substrate even if the substrate has an uneven surface by a method wherein the substrate is covered with a resin. CONSTITUTION:The uneven pattern layer 2 is formed on an oxide film 2 on the semiconductor substrate 1. The resin layer 3 is provided to make the surface to be flat, and a resist 4 is applied on it. Because the resist 4 is flat, so that contact print can be performed easily. A mask is adhered and exposure and developement are performed. The resin layer 3 and the pattern layer 2 are etched in accordance with the resist mask. Finally the resist 4, the resin layer 3 are removed to obtain the prescribed pattern 2. The resin layer 3 may be utilized as an insulating layer. In this case, a thermosetting resin having the setting temperature higher than the melting temperature is used, and after the solution of the resin is applied on the uneven surface, it is heated at a temperature higher than the melting temperature to be set.
JP15418779A 1979-11-30 1979-11-30 Formation of pattern Pending JPS5678122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15418779A JPS5678122A (en) 1979-11-30 1979-11-30 Formation of pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15418779A JPS5678122A (en) 1979-11-30 1979-11-30 Formation of pattern

Publications (1)

Publication Number Publication Date
JPS5678122A true JPS5678122A (en) 1981-06-26

Family

ID=15578732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15418779A Pending JPS5678122A (en) 1979-11-30 1979-11-30 Formation of pattern

Country Status (1)

Country Link
JP (1) JPS5678122A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04226013A (en) * 1990-04-18 1992-08-14 Internatl Business Mach Corp <Ibm> Imaging exposure device and exposure method
JP2006222081A (en) * 2005-02-08 2006-08-24 General Electric Canada Co Disconnector switch

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04226013A (en) * 1990-04-18 1992-08-14 Internatl Business Mach Corp <Ibm> Imaging exposure device and exposure method
JP2006222081A (en) * 2005-02-08 2006-08-24 General Electric Canada Co Disconnector switch

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