JPS54107676A - Manufacture for semiconductor device - Google Patents

Manufacture for semiconductor device

Info

Publication number
JPS54107676A
JPS54107676A JP1473178A JP1473178A JPS54107676A JP S54107676 A JPS54107676 A JP S54107676A JP 1473178 A JP1473178 A JP 1473178A JP 1473178 A JP1473178 A JP 1473178A JP S54107676 A JPS54107676 A JP S54107676A
Authority
JP
Japan
Prior art keywords
pattern
mask
normal
shape
pattern width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1473178A
Other languages
Japanese (ja)
Inventor
Masaru Yoshino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1473178A priority Critical patent/JPS54107676A/en
Publication of JPS54107676A publication Critical patent/JPS54107676A/en
Pending legal-status Critical Current

Links

Landscapes

  • Weting (AREA)

Abstract

PURPOSE: To accurately form the shape of the edge part for the fine pattern of around 1 to 5μm, with normal pattern width in normal mask alignment unit.
CONSTITUTION: Poly Si 3 and SiO2 4 are laminated on the SiO2 2 on the Si substrate 1. The resist mask 5 having the normal pattern width a and b is formed and the film 4 is etched, eliminating the mask. The resist mask 6 having the normal pattern width c and d is again formed, the film 3 is etched, the mask is eliminated, forming the fine pattern of the pattern width e = 1 to 5 μm. Since the sidths b to d are great enough not to be subjected to the interferrence due to the adjacent pattern, the shape is not destructed and the pattern having sure shape can be formed.
COPYRIGHT: (C)1979,JPO&Japio
JP1473178A 1978-02-10 1978-02-10 Manufacture for semiconductor device Pending JPS54107676A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1473178A JPS54107676A (en) 1978-02-10 1978-02-10 Manufacture for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1473178A JPS54107676A (en) 1978-02-10 1978-02-10 Manufacture for semiconductor device

Publications (1)

Publication Number Publication Date
JPS54107676A true JPS54107676A (en) 1979-08-23

Family

ID=11869264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1473178A Pending JPS54107676A (en) 1978-02-10 1978-02-10 Manufacture for semiconductor device

Country Status (1)

Country Link
JP (1) JPS54107676A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4911577A (en) * 1972-06-01 1974-02-01

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4911577A (en) * 1972-06-01 1974-02-01

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