JPS567449A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS567449A JPS567449A JP8307679A JP8307679A JPS567449A JP S567449 A JPS567449 A JP S567449A JP 8307679 A JP8307679 A JP 8307679A JP 8307679 A JP8307679 A JP 8307679A JP S567449 A JPS567449 A JP S567449A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- high concentration
- substrate
- wiring
- constitution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To integrate a device to a high degree by means of supplying line voltage through a semiconductor thin layer with high concentration by a method wherein a MOSFET is formed into a gas phase epitaxial layer made up on a one-conduction type semiconductor substrate through the high concentration layer. CONSTITUTION:An Sb diffusion layer 2 with high concentration in approximate 10<2>-10<6> times of an n-type Si substrate 1 and a p diffusion layer 3 are formed on the substrate 1. An n epitaxial layer 4 is stacked, and an n<+>-layer 5 is made up and connected to the n-layer 3. A p-type source 6 and a drain 7 are formed, an n<+> connecting layer 9 is built up, and Al electrodes 8, 10-12 are formed. According to this constitution, a device can be integrated without needing the wiring of Al wiring for a power source on a chip, and the voltage drop of the power source due to a resistance component of the buried layer 2 is extremely little.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8307679A JPS567449A (en) | 1979-06-29 | 1979-06-29 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8307679A JPS567449A (en) | 1979-06-29 | 1979-06-29 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS567449A true JPS567449A (en) | 1981-01-26 |
JPS6225260B2 JPS6225260B2 (en) | 1987-06-02 |
Family
ID=13792078
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8307679A Granted JPS567449A (en) | 1979-06-29 | 1979-06-29 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS567449A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62181474U (en) * | 1986-05-12 | 1987-11-18 |
-
1979
- 1979-06-29 JP JP8307679A patent/JPS567449A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6225260B2 (en) | 1987-06-02 |
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