JPS645064A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS645064A
JPS645064A JP62160619A JP16061987A JPS645064A JP S645064 A JPS645064 A JP S645064A JP 62160619 A JP62160619 A JP 62160619A JP 16061987 A JP16061987 A JP 16061987A JP S645064 A JPS645064 A JP S645064A
Authority
JP
Japan
Prior art keywords
layer
type
sbd
polycrystalline silicon
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62160619A
Other languages
Japanese (ja)
Inventor
Naomi Owada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62160619A priority Critical patent/JPS645064A/en
Publication of JPS645064A publication Critical patent/JPS645064A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To increase a series resistance value without increasing the size of a memory cell by a method wherein a polycrystalline silicon resistor is formed in a trench provided between the Schottky barrier diode region and the transistor region of a bipolar ECL-RAM. CONSTITUTION:Two n<+>type buried layers 2 and 2A which are separated from each other by an n<-->type epitaxial layer 3 formed on a p-type semiconductor substrate 1 are formed between the layer 3 and the substrate 1. A Schottky barrier diode (SBD) is formed on the surface of an n<->type epitaxial layer 10 above the layer 2A. A trench reaching the layer 2 is formed in the layer 3 on the layer 2 and on the SBD side and filled with an n<->type polycrystalline silicon layer 6. As the specific resistivity of the layer 3 is large, a current is applied to the SBD through the layer 6 and an n<+>type diffused layer 9 on the surface of the layer 6.
JP62160619A 1987-06-26 1987-06-26 Semiconductor integrated circuit device Pending JPS645064A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62160619A JPS645064A (en) 1987-06-26 1987-06-26 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62160619A JPS645064A (en) 1987-06-26 1987-06-26 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS645064A true JPS645064A (en) 1989-01-10

Family

ID=15718849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62160619A Pending JPS645064A (en) 1987-06-26 1987-06-26 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS645064A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012028474A (en) * 2010-07-21 2012-02-09 Panasonic Corp Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012028474A (en) * 2010-07-21 2012-02-09 Panasonic Corp Semiconductor device and manufacturing method thereof

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