JPS5734356A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5734356A JPS5734356A JP11001580A JP11001580A JPS5734356A JP S5734356 A JPS5734356 A JP S5734356A JP 11001580 A JP11001580 A JP 11001580A JP 11001580 A JP11001580 A JP 11001580A JP S5734356 A JPS5734356 A JP S5734356A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- buried
- type
- substrate
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 4
- 239000003990 capacitor Substances 0.000 abstract 1
- 239000004020 conductor Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To enable to obtain highly integrated circuit as well as to make them suitable for a D/A converter and the like by a method wherein a two-conductor type buried impurity layer, to be used for a passive element or a wiring, is buried at the lower part of the one-conductive type substrate constituting an active element on the main surface. CONSTITUTION:For example, a p<+> type buried layer 2 is formed on an n type substrate 1a, an n type layer 1b is epitaxially grown and after the buried layer 2 has been connected using p<++> layers 3a and 3b, an MOSFET, for example, is formed on the surface of the epitaxial layer 1b. The substrate 1a is connected to a positive power source and the buried layer 2 is utilized as a resistor by biassing it negatively. A wiring layer is formed by turning the buried layer 2 to p<++> type. Also, when the buried p<++> layer 2 is connected with the diffusion layer 3a only, their junction capacity can be utilized as a capacitor. Thus, the passive element and the wiring layer requiring a large area can be formed in the inner part of the substrate 1 and this enables to form a high density D/A converter and the like which will be used in combination with a plurality of resistance elements, for example.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11001580A JPS5734356A (en) | 1980-08-11 | 1980-08-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11001580A JPS5734356A (en) | 1980-08-11 | 1980-08-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5734356A true JPS5734356A (en) | 1982-02-24 |
Family
ID=14524954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11001580A Pending JPS5734356A (en) | 1980-08-11 | 1980-08-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5734356A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6274422B1 (en) | 1998-04-13 | 2001-08-14 | Nec Corporation | Method for manufacturing a semiconductor device |
| US7455533B2 (en) | 2004-11-19 | 2008-11-25 | Sharp Kabushiki Kaisha | Method for producing printed wiring board |
-
1980
- 1980-08-11 JP JP11001580A patent/JPS5734356A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6274422B1 (en) | 1998-04-13 | 2001-08-14 | Nec Corporation | Method for manufacturing a semiconductor device |
| US7455533B2 (en) | 2004-11-19 | 2008-11-25 | Sharp Kabushiki Kaisha | Method for producing printed wiring board |
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