JPS6225260B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power supply structure for a MOS transistor.

Conventional MOS transistor especially P channel
As a method of supplying power to MOS transistors, the power was supplied to a highly doped N-type diffusion layer called a channel stopper region on an N-type substrate through aluminum wiring routed around the integrated circuit chip from a power supply pad. However, the presence of the channel stopper region increases the area occupied by one transistor, which limits the ability to increase the integration and speed of MOS transistor integrated circuits. Therefore,
As a method of removing the channel stopper, that is, the highly doped N-type diffusion layer, and supplying power to each MOS transistor, it is possible to supply power directly from the power supply pad to each MOS transistor through aluminum wiring, for example. It will be done. however,
Due to the trend toward higher integration, the power supply method using aluminum wiring to integrated circuits with more than 10,000 elements requires a large area of the aluminum wiring within the integrated circuit chip, making it impossible to achieve high integration. It's inappropriate.

Another method for supplying power is to provide a highly doped N-type diffusion layer in an area other than the transistor area in the integrated circuit chip, that is, in the wiring area, and use the highly doped N-type diffusion layer as wiring for power supply. Conceivable. However, due to the reduction in wiring area due to high integration and restrictions due to high concentration P-type diffusion wiring within the wiring area, the "length to width ratio" of the high concentration N-type diffusion layer is large, that is, the Even with the concentration N-type diffusion layer, only the high-resistance diffusion layer has to be used as wiring for power supply, which causes a voltage drop in the power supply, making it impossible to increase the speed of the integrated circuit, which is inappropriate.

An object of the present invention is to eliminate the above-mentioned drawbacks and to obtain a power supply structure suitable for high integration.

That is, according to the present invention, there is provided a semiconductor substrate of one conductivity type and a semiconductor vapor phase growth layer formed thereon via a high concentration semiconductor thin layer, and a MOS type field effect transistor is formed in the semiconductor vapor phase growth layer. A semiconductor device is obtained in which a semiconductor element such as the above is formed and a power supply voltage is supplied to the semiconductor element through a highly doped semiconductor layer.

According to the present invention, the speed and integration of the integrated circuit can be increased, and power can be reliably supplied to each MOS transistor.

The present invention will be described below with reference to the drawings, taking an N-type silicon substrate as an example. Of course, the same explanation holds true for P-type silicon substrates as well.

The figure shows one embodiment of the present invention. That is, as shown in Fig. 1, the N type has 5×10 ¹⁴ cm ^-3 ~
On the surface of a silicon substrate 1 with an impurity concentration of 3×10 ¹⁵ cm ^-3, N-type impurities with different diffusion rates, such as antimony as an impurity with a slow diffusion rate and phosphorus as an impurity with a fast diffusion rate, are added.
An antimony diffusion layer 2 and a phosphorus diffusion layer 3 each having a concentration approximately 10 ² to 10 ⁶ times higher are diffused (hereinafter referred to as buried layer 2 and buried layer 3). After diffusing the buried layers 2 and 3, as shown in FIG. 2, an N-type impurity concentration of 5×10 ¹⁴ cm ^-3 is placed on the N-type silicon substrate 1.
An epitaxial layer 4 of ~3×10 ¹⁵ cm ⁻³ is formed. That is, the structure is such that the heavily doped N-type buried layers 2 and 3 are sandwiched between the N-type silicon substrate 1 and the N-type epitaxial layer 4. Next, as shown in Figure 3, a high concentration of N is applied to the lower part of the power supply pad.
By diffusing the type diffusion layer 5, a high concentration N type buried layer 3 is formed.
Establish continuity with. Thereafter, as shown in FIG. 4, a P-type source region 6 and a P-type drain region 7 of a MOS transistor are formed on the surface of the N-type epitaxial layer 4. A power supply voltage is supplied by an aluminum electrode 8 that will be formed later on the oxide film 13. At this time, in order to make ohmic contact between the aluminum electrode 8 and the epitaxial layer 4, a high concentration of N is applied.
A mold diffusion layer 9 is formed. Next, high concentration N type diffusion layer 5
A power source lead aluminum electrode 10 and other aluminum electrodes 11 and 12 are formed thereon.

As described above, according to the present invention, there is no need to route the power supply Al wiring over the integrated circuit chip as in the conventional case, and high integration can be achieved. Furthermore, since the channel stopper region is removed and the "length-to-width ratio" of the buried layer 2 between the N-type silicon substrate and the N-type epitaxial layer is small, the voltage drop in the power supply due to the resistance component of the buried layer 2 is reduced. It can also be made extremely small, making it possible to increase the speed of integrated circuits.

As described above, by the method of supplying power to a MOS transistor of the present invention, it is possible to further increase the degree of integration and speed of a MOS IC. In this embodiment, a P-channel MOS has been described, but it goes without saying that the present invention can also be applied to N-channel MOS and complementary MOS transistors.

[Brief explanation of the drawing]

1 to 4 are cross-sectional views showing one embodiment of the present invention in the order of manufacturing steps, and in particular, FIG. 4 is a cross-sectional view of a P-channel MOS transistor obtained by applying the present invention. DESCRIPTION OF SYMBOLS 1... N-type silicon substrate, 2... Antimony buried layer, 3... Phosphorus buried layer, 4... N-type epitaxial layer, 5... High concentration phosphorus diffusion layer, 6...
... Lease region, 7 ... Drain region, 8 ... Source electrode, 9 ... Contact diffusion layer, 10 ... Leading aluminum electrode for power supply, 11 ... Drain electrode, 1
2...Gate electrode.

Claims (1)

[Claims] 1. In a semiconductor device having a semiconductor layer of one conductivity type on a semiconductor substrate of one conductivity type, and a field effect transistor formed in the semiconductor layer, a high concentration semiconductor thin layer is provided between the semiconductor substrate and the semiconductor layer. 1. A semiconductor device comprising: a thin layer of highly concentrated semiconductor;