JPS5669835A - Method for forming thin film pattern - Google Patents

Method for forming thin film pattern

Info

Publication number
JPS5669835A
JPS5669835A JP14576079A JP14576079A JPS5669835A JP S5669835 A JPS5669835 A JP S5669835A JP 14576079 A JP14576079 A JP 14576079A JP 14576079 A JP14576079 A JP 14576079A JP S5669835 A JPS5669835 A JP S5669835A
Authority
JP
Japan
Prior art keywords
film
whose
pattern
layer
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14576079A
Other languages
English (en)
Inventor
Kohei Kishi
Hiroaki Kato
Masataka Matsuura
Tomio Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JAPAN ELECTRONIC IND DEV ASSOC<JEIDA>
Sharp Corp
Original Assignee
JAPAN ELECTRONIC IND DEV ASSOC<JEIDA>
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JAPAN ELECTRONIC IND DEV ASSOC<JEIDA>, Sharp Corp filed Critical JAPAN ELECTRONIC IND DEV ASSOC<JEIDA>
Priority to JP14576079A priority Critical patent/JPS5669835A/ja
Priority to GB8035653A priority patent/GB2065379B/en
Priority to DE19803041839 priority patent/DE3041839A1/de
Publication of JPS5669835A publication Critical patent/JPS5669835A/ja
Priority to US06/403,325 priority patent/US4451554A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
    • H05K3/048—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • ing And Chemical Polishing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
JP14576079A 1979-11-09 1979-11-09 Method for forming thin film pattern Pending JPS5669835A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP14576079A JPS5669835A (en) 1979-11-09 1979-11-09 Method for forming thin film pattern
GB8035653A GB2065379B (en) 1979-11-09 1980-11-06 Method of forming a thin-film pattern
DE19803041839 DE3041839A1 (de) 1979-11-09 1980-11-06 Verfahren zur bildung eines fuennfilmschemas
US06/403,325 US4451554A (en) 1979-11-09 1982-07-30 Method of forming thin-film pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14576079A JPS5669835A (en) 1979-11-09 1979-11-09 Method for forming thin film pattern

Publications (1)

Publication Number Publication Date
JPS5669835A true JPS5669835A (en) 1981-06-11

Family

ID=15392518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14576079A Pending JPS5669835A (en) 1979-11-09 1979-11-09 Method for forming thin film pattern

Country Status (4)

Country Link
US (1) US4451554A (ja)
JP (1) JPS5669835A (ja)
DE (1) DE3041839A1 (ja)
GB (1) GB2065379B (ja)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3139069A1 (de) * 1981-10-01 1983-04-14 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum herstellen von strukturierten schichten auf der oberflaeche eines halbleiterkoerpers
US4654295A (en) * 1983-12-05 1987-03-31 Energy Conversion Devices, Inc. Method of making short channel thin film field effect transistor
US4687541A (en) * 1986-09-22 1987-08-18 Rockwell International Corporation Dual deposition single level lift-off process
DE3806287A1 (de) * 1988-02-27 1989-09-07 Asea Brown Boveri Aetzverfahren zur strukturierung einer mehrschicht-metallisierung
US4964945A (en) * 1988-12-09 1990-10-23 Minnesota Mining And Manufacturing Company Lift off patterning process on a flexible substrate
US5830533A (en) * 1991-05-28 1998-11-03 Microelectronics And Computer Technology Corporation Selective patterning of metallization on a dielectric substrate
JPH07131155A (ja) * 1993-11-01 1995-05-19 Hitachi Ltd 多層配線基板の製造方法及び多層配線基板
US5916733A (en) * 1995-12-11 1999-06-29 Kabushiki Kaisha Toshiba Method of fabricating a semiconductor device
US6342681B1 (en) * 1997-10-15 2002-01-29 Avx Corporation Surface mount coupler device
JP2000357671A (ja) * 1999-04-13 2000-12-26 Sharp Corp 金属配線の製造方法
US8158530B2 (en) * 2008-09-10 2012-04-17 Globalfoundries Inc. Methods for retaining metal-comprising materials using liquid chemistry dispense systems from which oxygen has been removed
WO2012030407A1 (en) * 2010-09-03 2012-03-08 Tetrasun, Inc. Fine line metallization of photovoltaic devices by partial lift-off of optical coatings
US9508887B2 (en) * 2012-10-25 2016-11-29 Tetrasun, Inc. Methods of forming solar cells
US9673341B2 (en) 2015-05-08 2017-06-06 Tetrasun, Inc. Photovoltaic devices with fine-line metallization and methods for manufacture
CN109410757A (zh) 2017-08-15 2019-03-01 元太科技工业股份有限公司 挠性显示装置及其边框元件
SE541452C2 (en) * 2018-02-22 2019-10-08 Solibro Res Ab Method for patterning a surface with a metal by controlling the generation of cracks or gaps in a deposited metal layer
CN110775940B (zh) * 2019-10-31 2023-08-15 潍坊歌尔微电子有限公司 Mems传感器组件制造方法、以及以该法制造的mems传感器组件

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4845868A (ja) * 1971-10-15 1973-06-30
JPS4999274A (ja) * 1973-01-25 1974-09-19
JPS5045571A (ja) * 1973-08-25 1975-04-23

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA918297A (en) * 1969-09-24 1973-01-02 Tanimura Shigeru Semiconductor device and method of making
DE2040180B2 (de) * 1970-01-22 1977-08-25 Intel Corp, Mountain View, Calif. (V.St.A.) Verfahren zur verhinderung von mechanischen bruechen einer duennen, die oberflaeche eines halbleiterkoerpers ueberdeckende isolierschichten ueberziehenden elektrisch leitenden schicht
NL163370C (nl) * 1972-04-28 1980-08-15 Philips Nv Werkwijze voor het vervaardigen van een halfgeleider- inrichting met een geleiderpatroon.
DE2432719B2 (de) * 1974-07-08 1977-06-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zum erzeugen von feinen strukturen aus aufdampfbaren materialien auf einer unterlage und anwendung des verfahrens
US4218532A (en) * 1977-10-13 1980-08-19 Bell Telephone Laboratories, Incorporated Photolithographic technique for depositing thin films
US4232059A (en) * 1979-06-06 1980-11-04 E-Systems, Inc. Process of defining film patterns on microelectronic substrates by air abrading

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4845868A (ja) * 1971-10-15 1973-06-30
JPS4999274A (ja) * 1973-01-25 1974-09-19
JPS5045571A (ja) * 1973-08-25 1975-04-23

Also Published As

Publication number Publication date
DE3041839A1 (de) 1981-05-27
US4451554A (en) 1984-05-29
GB2065379A (en) 1981-06-24
GB2065379B (en) 1983-12-14

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