JPS5662354A - Hybrid type semiconductor integrated circuit device - Google Patents

Hybrid type semiconductor integrated circuit device

Info

Publication number
JPS5662354A
JPS5662354A JP13915779A JP13915779A JPS5662354A JP S5662354 A JPS5662354 A JP S5662354A JP 13915779 A JP13915779 A JP 13915779A JP 13915779 A JP13915779 A JP 13915779A JP S5662354 A JPS5662354 A JP S5662354A
Authority
JP
Japan
Prior art keywords
integrated circuit
base board
type semiconductor
semiconductor integrated
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13915779A
Other languages
Japanese (ja)
Inventor
Hideyuki Ozaki
Kazuhiro Shimotori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP13915779A priority Critical patent/JPS5662354A/en
Publication of JPS5662354A publication Critical patent/JPS5662354A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To make an improved density of the installed semiconductor device on the base board by a method wherein a capacity of the decoupling is composed in a semiconductor base board having an integrated circuit thereon. CONSTITUTION:An integrated circuit is constructed on the surface of the semiconductor base board 1. Electrode 1 on the insulation film 14 is connected to the power supply pad 9 and the power supply main line 13. The electrode 19 on the insulation film 18 is connected to the ground pad 4 and the ground main line 12. A decoupling capacity is constituted by the electrodes 15, 19 and insulation film 18. The decoupling capacitor is arranged on the base board 1, so that a density of its installation on the base board may be increased and at the same time a reliability of the device may be improved as well.
JP13915779A 1979-10-25 1979-10-25 Hybrid type semiconductor integrated circuit device Pending JPS5662354A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13915779A JPS5662354A (en) 1979-10-25 1979-10-25 Hybrid type semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13915779A JPS5662354A (en) 1979-10-25 1979-10-25 Hybrid type semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5662354A true JPS5662354A (en) 1981-05-28

Family

ID=15238896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13915779A Pending JPS5662354A (en) 1979-10-25 1979-10-25 Hybrid type semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5662354A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923541A (en) * 1982-07-30 1984-02-07 Nec Corp Semiconductor device
JPS5948090U (en) * 1982-09-30 1984-03-30 松下電工株式会社 Memory unit of sequence control device
JPS60192359A (en) * 1984-03-14 1985-09-30 Nec Corp Semiconductor memory
JPS63177056U (en) * 1987-05-01 1988-11-16
US6303457B1 (en) 1996-02-13 2001-10-16 Todd Alan Christensen Integrated circuit having integral decoupling capacitor
US7288844B2 (en) 2002-06-12 2007-10-30 Nec Corporation Semiconductor device, semiconductor circuit and method for producing semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923541A (en) * 1982-07-30 1984-02-07 Nec Corp Semiconductor device
JPS5948090U (en) * 1982-09-30 1984-03-30 松下電工株式会社 Memory unit of sequence control device
JPH0346552Y2 (en) * 1982-09-30 1991-10-01
JPS60192359A (en) * 1984-03-14 1985-09-30 Nec Corp Semiconductor memory
JPH0476215B2 (en) * 1984-03-14 1992-12-03 Nippon Electric Co
JPS63177056U (en) * 1987-05-01 1988-11-16
US6303457B1 (en) 1996-02-13 2001-10-16 Todd Alan Christensen Integrated circuit having integral decoupling capacitor
US7288844B2 (en) 2002-06-12 2007-10-30 Nec Corporation Semiconductor device, semiconductor circuit and method for producing semiconductor device

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