JPS5580343A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5580343A
JPS5580343A JP15443078A JP15443078A JPS5580343A JP S5580343 A JPS5580343 A JP S5580343A JP 15443078 A JP15443078 A JP 15443078A JP 15443078 A JP15443078 A JP 15443078A JP S5580343 A JPS5580343 A JP S5580343A
Authority
JP
Japan
Prior art keywords
power supply
terminal
bias
pad
case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15443078A
Other languages
Japanese (ja)
Inventor
Junichi Inoue
Nobuaki Ieda
Tsuneo Mano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP15443078A priority Critical patent/JPS5580343A/en
Publication of JPS5580343A publication Critical patent/JPS5580343A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To make a bias terminal unnecessary by enclosing in a case an IC which starts operation when a bias voltage is applied and connecting a bias power supply inside the case.
CONSTITUTION: Operation power supply terminals TD and TS only are projected on the lower side of case 1. Capacity element 14 consisting of electrodes 12 and 13 placed on both sides of dielectric layer 11 is enclosed inside case 1. Next, on bias power supply pad PB provided on electrode 13 is fitted semiconductor chip 2 having on its surface operation power supply pads PD and PS via bias power supply electrode EB. Sandwiching chip 2 on electrode EB, insulation layer 3 having operation power supply connection relay terminals TD' and TS' is provided. Terminal TD is connected to terminal TD' and pad PD by using lead lines LD and LD'. Terminal TS is connected to terminal TS' and pad PS by using lead lines LS and LS', and it is also connected to pad PB of element 14. By this, a bias terminal becomes unnecessary and the device is simplified.
COPYRIGHT: (C)1980,JPO&Japio
JP15443078A 1978-12-12 1978-12-12 Semiconductor device Pending JPS5580343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15443078A JPS5580343A (en) 1978-12-12 1978-12-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15443078A JPS5580343A (en) 1978-12-12 1978-12-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5580343A true JPS5580343A (en) 1980-06-17

Family

ID=15584000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15443078A Pending JPS5580343A (en) 1978-12-12 1978-12-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5580343A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992005559A1 (en) * 1990-09-17 1992-04-02 Kabushiki Kaisha Toshiba Semiconductor storing device
US5519654A (en) * 1990-09-17 1996-05-21 Kabushiki Kaisha Toshiba Semiconductor memory device with external capacitor to charge pump in an EEPROM circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992005559A1 (en) * 1990-09-17 1992-04-02 Kabushiki Kaisha Toshiba Semiconductor storing device
US5519654A (en) * 1990-09-17 1996-05-21 Kabushiki Kaisha Toshiba Semiconductor memory device with external capacitor to charge pump in an EEPROM circuit

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