JPS63177056U - - Google Patents
Info
- Publication number
- JPS63177056U JPS63177056U JP6630387U JP6630387U JPS63177056U JP S63177056 U JPS63177056 U JP S63177056U JP 6630387 U JP6630387 U JP 6630387U JP 6630387 U JP6630387 U JP 6630387U JP S63177056 U JPS63177056 U JP S63177056U
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- line wiring
- layer
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000003990 capacitor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案の一実施例構成図である。
１……ｎ型基板、２……ｐ型ソース、ドレイン
領域、３……ｎ型ソース、ドレイン領域、４，５
……ゲート電極、７，９……金属配線層、１１…
…電源ライン配線層、１２……接地ライン配線層
、１３……誘電体からなる絶縁体層。
FIG. 1 is a configuration diagram of an embodiment of the present invention. 1... N-type substrate, 2... P-type source, drain region, 3... N-type source, drain region, 4, 5
...Gate electrode, 7, 9...Metal wiring layer, 11...
...Power line wiring layer, 12... Ground line wiring layer, 13... Insulator layer made of dielectric material.
Claims (1)
て、多層配線層の外側２層の一方を電源ライン配
線層、他方を接地ライン配線層とし、両者の間に
誘電体層を設けて電源ライン配線層と接地ライン
配線層間にコンデンサを形成することを特徴とす
る半導体集積回路装置。 In a semiconductor integrated circuit device having a multilayer wiring layer, one of the two outer layers of the multilayer wiring layer is a power line wiring layer and the other is a grounding line wiring layer, and a dielectric layer is provided between the two to connect the power line wiring layer and the grounding layer. A semiconductor integrated circuit device characterized in that a capacitor is formed between line wiring layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6630387U JPS63177056U (en) | 1987-05-01 | 1987-05-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6630387U JPS63177056U (en) | 1987-05-01 | 1987-05-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63177056U true JPS63177056U (en) | 1988-11-16 |
Family
ID=30904185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6630387U Pending JPS63177056U (en) | 1987-05-01 | 1987-05-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63177056U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5662354A (en) * | 1979-10-25 | 1981-05-28 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Hybrid type semiconductor integrated circuit device |
| JPS60170963A (en) * | 1984-02-16 | 1985-09-04 | Nec Corp | Semiconductor integrated circuit device |
-
1987
- 1987-05-01 JP JP6630387U patent/JPS63177056U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5662354A (en) * | 1979-10-25 | 1981-05-28 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Hybrid type semiconductor integrated circuit device |
| JPS60170963A (en) * | 1984-02-16 | 1985-09-04 | Nec Corp | Semiconductor integrated circuit device |