JPH0463653U - - Google Patents
Info
- Publication number
- JPH0463653U JPH0463653U JP10733390U JP10733390U JPH0463653U JP H0463653 U JPH0463653 U JP H0463653U JP 10733390 U JP10733390 U JP 10733390U JP 10733390 U JP10733390 U JP 10733390U JP H0463653 U JPH0463653 U JP H0463653U
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor device
- spiral
- showing
- sectional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 2
- 230000005294 ferromagnetic effect Effects 0.000 claims 1
- 239000003302 ferromagnetic material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案の一実施例の半導体装置を示す
上面図、第２図は第１図の−′線に沿つて切
断して見た断面図、第３図は第２の半導体装置に
電流を印加した状態を示す断面図、第４図は本考
案の他の実施例の上面図、第５図は第４図の−
′線の断面図、第６図は第５図の電流印加状態
を示す断面図、第７図は従来の半導体装置を示す
上面図、第８図は第７図の２−２′線の断面
図、第９図は第８図の電流印加状態を示す断面図
である。
１……第一の配線、２……第二の配線、３……
強磁性体の第三の配線、４……コンタクト、５…
…フイールド領域、６……基板、７，８……層間
絶縁膜。
FIG. 1 is a top view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line -' in FIG. 1, and FIG. FIG. 4 is a top view of another embodiment of the present invention, and FIG. 5 is a cross-sectional view showing a state in which a current is applied.
6 is a sectional view showing the current application state in FIG. 5, FIG. 7 is a top view showing a conventional semiconductor device, and FIG. 8 is a sectional view taken along line 2-2 ' in FIG. 7. 9 are cross-sectional views showing the current application state of FIG. 8. 1...First wiring, 2...Second wiring, 3...
Third wiring of ferromagnetic material, 4... Contact, 5...
... Field region, 6 ... Substrate, 7, 8 ... Interlayer insulating film.
Claims (1)
うず巻状の第一の配線と、その端部を側方に取出
す第二の配線とを設け、前記第一の配線の上また
下に、前記第一の配線と前記第二の配線とは絶縁
された強磁性体層を設けたことを特徴とする半導
体装置。 As an inductance element on a semiconductor substrate,
A spiral-shaped first wiring and a second wiring whose end portion is taken out to the side are provided, and the first wiring and the second wiring are arranged above and below the first wiring. A semiconductor device comprising an insulated ferromagnetic layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10733390U JPH0463653U (en) | 1990-10-12 | 1990-10-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10733390U JPH0463653U (en) | 1990-10-12 | 1990-10-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0463653U true JPH0463653U (en) | 1992-05-29 |
Family
ID=31853797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10733390U Pending JPH0463653U (en) | 1990-10-12 | 1990-10-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0463653U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7414506B2 (en) | 2003-12-22 | 2008-08-19 | Nec Electronics Corporation | Semiconductor integrated circuit and fabrication method thereof |
-
1990
- 1990-10-12 JP JP10733390U patent/JPH0463653U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7414506B2 (en) | 2003-12-22 | 2008-08-19 | Nec Electronics Corporation | Semiconductor integrated circuit and fabrication method thereof |