JPH0395651U - - Google Patents
Info
- Publication number
- JPH0395651U JPH0395651U JP174090U JP174090U JPH0395651U JP H0395651 U JPH0395651 U JP H0395651U JP 174090 U JP174090 U JP 174090U JP 174090 U JP174090 U JP 174090U JP H0395651 U JPH0395651 U JP H0395651U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- metal wiring
- internal circuits
- insulating film
- blocks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第１図ａ，ｂは本考案の一実施例の平面図及び
Ａ−Ａ′線断面図、第２図ａ，ｂは従来の半導体
装置の一例の平面図及びＢ−Ｂ′線断面図である
。
１……シリコン基板、２……酸化膜、３……層
間絶縁膜、４……金属配線、５ａ，５ｂ……付加
の配線、６……第１の内部回路、７……第２の内
部回路、８……溝。
1A and 1B are a plan view and a sectional view taken along the line A-A' of an embodiment of the present invention, and FIGS. 2A and 2B are a plan view and a sectional view taken along the line B-B' of an example of a conventional semiconductor device. be. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Oxide film, 3... Interlayer insulating film, 4... Metal wiring, 5a, 5b... Additional wiring, 6... First internal circuit, 7... Second interior Circuit, 8...groove.
Claims (1)
され、金属配線で前記内部回路間が接続されてい
る半導体装置において、前記金属配線の下方に該
金属配線と垂直方向に少しの間隔をおいてほぼ平
行に、かつどの素子にも接続しない２本の付加の
配線を絶縁膜を介して設けたことを特徴とする半
導体装置。 In a semiconductor device in which a plurality of blocks of internal circuits are formed on a semiconductor substrate, and the internal circuits are connected by metal wiring, a block of internal circuits is formed below the metal wiring in the perpendicular direction and approximately parallel to the metal wiring with a small distance therebetween. What is claimed is: 1. A semiconductor device comprising: a semiconductor device; and two additional wires not connected to any element, provided with an insulating film interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP174090U JPH0395651U (en) | 1990-01-12 | 1990-01-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP174090U JPH0395651U (en) | 1990-01-12 | 1990-01-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0395651U true JPH0395651U (en) | 1991-09-30 |
Family
ID=31505635
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP174090U Pending JPH0395651U (en) | 1990-01-12 | 1990-01-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0395651U (en) |
-
1990
- 1990-01-12 JP JP174090U patent/JPH0395651U/ja active Pending
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