JPS5658232A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5658232A
JPS5658232A JP13406979A JP13406979A JPS5658232A JP S5658232 A JPS5658232 A JP S5658232A JP 13406979 A JP13406979 A JP 13406979A JP 13406979 A JP13406979 A JP 13406979A JP S5658232 A JPS5658232 A JP S5658232A
Authority
JP
Japan
Prior art keywords
nonelectrolytic
plating
warpage
wafer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13406979A
Other languages
Japanese (ja)
Inventor
Toshio Yao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13406979A priority Critical patent/JPS5658232A/en
Publication of JPS5658232A publication Critical patent/JPS5658232A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemically Coating (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To lessen a wafer warpage when forming a glass film by a method wherein an electrode is made on the grooved surface of a substrate with a nonelectrolytic partial plating and an electrode is made on the whole grooveless reverse side with a nonelectrolytic plating. CONSTITUTION:A P-epitaxial layer 2 is provided on an N type si substrate 1 and then a P-N junction 3 is made. A groove 4 is provided and Ni plated layers 6 and 7 are formed by providing a mask 8 and by performing a nonelectrolytic Ni plating. The mask is removed, a heat treatment is performed at the temperature of approximately 700 deg.C and a concaved curvature is obtained on the side of the laye 7 due to the residual stress of the Ni plted layer. Then, when a glass film is formed on the groove 4, a concaved curvature is obtained on the side of the layer 7 due to the contractile force generated at the time of sintering and the warpage of a wafer is corrected. Next, Ni layers 6 and 7 are made by providing a mask again and by performing a nonelectrolytic Ni plating, and the substrate is cut at the grooved section and divided into pellets. With the above constitution being accomplished, the warpage of the wafer is reduced and an yield rate and workability of the device can be improved.
JP13406979A 1979-10-16 1979-10-16 Manufacture of semiconductor device Pending JPS5658232A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13406979A JPS5658232A (en) 1979-10-16 1979-10-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13406979A JPS5658232A (en) 1979-10-16 1979-10-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5658232A true JPS5658232A (en) 1981-05-21

Family

ID=15119643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13406979A Pending JPS5658232A (en) 1979-10-16 1979-10-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5658232A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58153384A (en) * 1982-03-05 1983-09-12 Asahi Chem Ind Co Ltd Magnetoelectricity conversion element and manufacture thereof
JPH10287980A (en) * 1997-04-17 1998-10-27 Hitachi Ltd Formation of electrode for semiconductor device
US7192848B2 (en) 2004-02-16 2007-03-20 Rohm Co., Ltd. Method for manufacturing mesa semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58153384A (en) * 1982-03-05 1983-09-12 Asahi Chem Ind Co Ltd Magnetoelectricity conversion element and manufacture thereof
JPH10287980A (en) * 1997-04-17 1998-10-27 Hitachi Ltd Formation of electrode for semiconductor device
US7192848B2 (en) 2004-02-16 2007-03-20 Rohm Co., Ltd. Method for manufacturing mesa semiconductor device

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